HYB3117405BJ-70.pdf 데이터시트 (총 26 페이지) - 파일 다운로드 HYB3117405BJ-70 데이타시트 다운로드

No Preview Available !

3.3V 4M x 4-Bit EDO-Dynamic RAM
HYB3116405BJ/BT(L) -50/-60/-70
HYB3117405BJ/BT(L) -50/-60/-70
Advanced Information
4 194 304 words by 4-bit organization
0 to 70 °C operating temperature
Performance
tRAC
tCAC
tAA
tRC
tHPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Hyper page mode (EDO)
cycle time
-50 -60 -70
50 60 70 ns
13 15 20 ns
25 30 35 ns
84 104 124 ns
20 25 30 ns
Single + 3.3 V (± 0.3V ) supply
Low power dissipation
max. 396 active mW (HYB3117405BJ/BT-50)
max. 363 active mW (HYB3117405BJ/BT-60)
max. 330 active mW (HYB3117405BJ/BT-70)
max. 360 active mW (HYB3116405BJ/BT-50)
max. 324 active mW (HYB3116405BJ/BT-60)
max. 288 active mW (HYB3116405BJ/BT-70)
7.2 mW standby (LV-TTL)
3.6 mW standby (LV-CMOS)
720 µW standby for L-version
Output unlatched at cycle end allows two-dimensional chip selection
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
Self Refresh and test mode
Hyper page mode (EDO) capability
All inputs, outputs and clocks fully TTL-compatible
2048 refresh cycles / 32 ms for HYB3117405
4096 refresh cycles / 64 ms for HYB3116405
Plastic Package:
P-SOJ-26/24-1 (300 mil)
P-TSOPII-26/24-1 (300mil)
Semiconductor Group
1
3.96

No Preview Available !

HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
The HYB 3116(7)405BJ/BT(L) is a 16MBit dynamic RAM organized as 4194304 words by 4-bits.
The HYB 3116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well
as advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 3116(7)405BJ/BT(L) to be packaged in a standard
SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct
interfacing with high-performance logic device families.The HYB3116405BTL parts have a very low
power „sleep mode“ supported by Self Refresh.
Ordering Information
Type
HYB 3117405BJ-50
HYB 3117405BJ-60
HYB 3117405BJ-70
HYB 3117405BT-50
HYB 3117405BT-60
HYB 3117405BT-70
HYB 3116405BJ-50
HYB 3116405BJ-60
HYB 3116405BJ-70
HYB 3116405BT-50
HYB 3116405BT-60
HYB 3116405BT-70
HYB 3116405BTL-50
HYB 3116405BTL-60
HYB 3116405BTL-70
Ordering Code
Q67100-Q1119
Q67100-Q1120
Q67100-Q1135
Q67100-Q1136
Q67100-Q1184
Q67100-Q1127
Q67100-Q1128
Q67100-Q1143
Q67100-Q1144
Q67100-Q1186
on request
on request
on request
Package
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
Descriptions
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
LP-DRAM (access time 50 ns)
LP-DRAM (access time 60 ns)
LP-DRAM (access time 70 ns)
Semiconductor Group
2

No Preview Available !

HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
Vcc
I/O1
I/O2
WE
RAS
N.C.
1
2
3
4
5
6
26 Vss Vcc 1
25 I/O4 I/O1 2
24 I/O3 I/O2 3
23 CAS WE 4
22 OE RAS 5
21 A9 A11 6
26 Vss
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
HYB3117405BJ/BT
A8
A7
A6
A5
A4
Vss
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
HYB3116405BJ/BT
A8
A7
A6
A5
A4
Vss
P-SOJ-26/24-1 (300mil)
P-TSOPII-26/24-1 (300mil)
Pin Configuration
Pin Names
A0 to A10
A0 to A11
A0 to A9
RAS
OE
I/O1 -I/O4
CAS
WE
VCC
VSS
N.C.
Row & Column Address Inputs for HYB3117405
Row Address Inputs for HYB3116405
Column Address Inputs for HYB3116405
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply (+ 3.3 V)
Ground (0 V)
not connected
Semiconductor Group
3

No Preview Available !

HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
I/O1 I/O2 I/O3 I/O4
WE
.CAS
&
No. 2 Clock
Generator
Data in
Buffer
4
Data out
Buffer
4
OE
Column
11 Address
A0 Buffer(11)
A1
A2
A3 Refresh
A4 Controller
A5
A6
11 Column
Decoder
Sense Amplifier
I/O Gating
4
A7 Refresh
A8 Counter (11)
A9
A10 11
2048
x4
Row
11 Address
Buffers(11)
Row
Memory Array
11 Decoder 2048 2048x2048x4
RAS
No. 1 Clock
Generator
Block Diagram for HYB3117405
Semiconductor Group
4

No Preview Available !

HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
I/O1 I/O2 I/O3 I/O4
WE
.CAS
&
No. 2 Clock
Generator
Data in
Buffer
4
Data out
Buffer
4
OE
Column
10 Address
A0 Buffer(10)
A1
10 Column
Decoder
A2
A3 Refresh
A4 Controller
A5
Sense Amplifier
I/O Gating
4
A6
A7 Refresh
A8 Counter (12)
A9
A10 12
1024
x4
A11 Row
Row
Memory Array
12 Address
12 Decoder 4096 4096x1024x4
Buffers(12)
RAS
No. 1 Clock
Generator
Block Diagram for HYB3116405
Semiconductor Group
5