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HT9302 Series
1-Memory/2-Memory Tone/Pulse Dialer
Features
Patent Number: 64097, 86474, 64529, 113235 (R.O.C.)
5424740 (U.S.A.)
· Universal specification
· Operating voltage: 2.0V~5.5V
· Low standby current
· Low memory retention current: 0.1mA (typ.)
· Tone/pulse switchable
· Interface with LCD driver
· 32 digits for redialing
· 32 digits for SA memory dialing
· One-key redialing
· Pause and P®T key for PBX
· 4´4 keyboard matrix
· 3.58MHz crystal or ceramic resonator
· Hand-free control
· Hold-line control
· Pause, P®T can be saved for redialing
· Lock function
· Resistor options
- M/B ratio
- Flash function and flash time
- Pause and P®T duration
- Pulse number
· HT9302A: 18-pin DIP package
HT9302B: 22-pin SKDIP package
HT9302C: 20-pin DIP package
HT9302D: 24-pin SKDIP package
HT9302G: 16-pin DIP package
General Description
The HT9302 series tone/pulse dialers are CMOS LSIs
for telecommunication systems. They are designed to
meet various dialing specifications through resistor op-
tion matrix.
The HT9302 series provide the pin-selected lock func-
tion, Hold-line, Hand-free and LCD dialing number
display interface, all of which are suitable for feature
phone applications. HT9302G is simpler than HT9302X
version. It provides only a redialing memory for simple
low-cost system applications.
Selection Table
Function
Part No.
HT9302x
HT9302A
HT9302B
HT9302C
HT9302D
HT9302G
HT9302G
Lock Function
(Pin Selection)
Ö
Ö
Ö
Ö
¾
Hold Line
Hand Free
LCD Interface
Package
(Normal version)
¾¾
ÖÖ
¾¾
ÖÖ
(Simple version)
¾¾
¾ 18 DIP
¾ 22 SKDIP
Ö 20 DIP
Ö 24 SKDIP
¾ 16 DIP
Rev. 1.20
1 September 30, 2002

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Block Diagram
HT9302 Series
C1
K ey
C o lu m n
C4
R1
K ey R ow
R4
X1
D iv id e r
X2
.SM
K ey
. u n c tio n
E ncoder
E ncoder
D ebounce
C lo c k
G e n e ra to r
C o n tro l
W RM
C o u n te r
ADDRL
SRAM
C heck
Tone
E ncoder
C o n v e rte r
Tone
O ut
P u ls e
O ut
C lo c k
C o n tro l
. la s h
M o d e In
H D /H .
M /B T im e r
LO C K
K e y to n e
G e n e ra to r
DOUT
C LO C K
D TM .
PO
XM U TE
HKS
H .I
HDI
HDO
H .O
M ODE
Pin Assignment
HT9302x normal version
C1
C2
C3
C4
LO C K
X1
X2
XM U TE
VSS
1 18
2 17
3 16
4 15
5 14
6 13
7 12
8 11
9 10
H T9302A
1 8 D IP -A
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
HDI
C1
C2
C3
C4
LO C K
X1
X2
XM U TE
VSS
H .I
1 22
2 21
3 20
4 19
5 18
6 17
7 16
8 15
9 14
10 13
11 12
H T9302B
2 2 S K D IP -A
HDO
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
H .O
C1
C2
C3
C4
LO C K
X1
X2
XM U TE
VSS
DOUT
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
H T9302C
2 0 D IP -A
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
C LO C K
HDI
C1
C2
C3
C4
LO C K
X1
X2
XM U TE
VSS
H .I
DOUT
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
H T9302D
2 4 S K D IP -A
HDO
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
H .O
C LO C K
HT9302G simple version
C1
C2
C3
X1
X2
XM U TE
VSS
VDD
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
H T9302G
1 6 D IP -A
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
Rev. 1.20
2 September 30, 2002

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Keyboard Information
H T 9 3 0 2 A /B /C /D
C1 C2 C3
R1 1
R2 4
R3 7
R 4 * /T
2
5
8
0
3
6
9
#
C4
SA
.
P
R
H T9302G
C1
R1 1
R2 4
R3 7
R 4 * /T
C2
2
5
8
0
C3 HKS
3
6.
9P
#R
HT9302 Series
Pin Description
Pin Name
I/O
Internal
Connection
Description
C1~C4
R1~R4
These pins form a 4´4 keyboard matrix which can perform keyboard input detec-
tion and dialing specification setting functions. When on-hook (HKS=high) all the
pins are set high. While off-hook the column group (C1~C4) remains low and the
row group (R1~R4) is set high for key input detection.
I/O CMOS IN/OUT An inexpensive single contact 4´4 keyboard can be used as an input device.
Pressing a key connects a single column to a single row, and actuates the system
oscillator that results in a dialing signal output. If more than two keys are pressed at
the same time, no response occurs. The key-in debounce time is 20ms. Refer to
the keyboard information for keyboard arrangement and to the functional descrip-
tion for dialing specification selection.
X1 I
The system oscillator consists of an inverter, a bias resistor and the necessary
load capacitor on chip. Connecting a standard 3.579545MHz crystal or ceramic
OSCILLATOR resonator to the X1 and X2 terminals can implement the oscillator function. The
X2 O
oscillator is turned off in the standby mode, and is actuated whenever a key-
board entry is detected.
XMUTE
XMUTE is an NMOS open drain structure pulled to VSS during dialing signal
O NMOS OUT transmission. Otherwise, it is an open circuit. The XMUTE is used to mute the
speech circuit when transmitting the dial signal.
HKS
This pin is used to monitor the status of the hook-switch and its combination
with HFI/HDI can control the PO pin output to make or break the line.
I
CMOS IN
HKS=VDD: On-hook state (PO=low). Except for HFI/HDI
(hand-free/hold-line control input), other functions are all disabled.
HKS=VSS: Off-hook state (PO=high). The chip is in the standby mode and
ready to receive the key input.
This pin is a CMOS output structure, which by receiving HKS and HFO/HDO
signals, control the dialer to connect or disconnect the telephone line.
PO outputs a low to break the line when HKS is high (on-hook) and HFO/HDO
PO O CMOS OUT is low. PO outputs a high to make the line when HKS is low (off-hook) or HFO is
high or HDO is high.
During the off-hook state, the pin also outputs the dialing pulse train in pulse
mode dialing. While in the tone mode, this pin is always high.
MODE
This is a three-state input/output pin, used for dialing mode selection whether
Tone mode or Pulse mode; 10pps/20pps.
MODE=VDD: Pulse mode, 10pps
I/O
CMOS IN/OUT
MODE=OPEN: Pulse mode, 20pps
MODE=VSS: Tone mode
During pulse mode dialing, switching this pin to the tone mode changes the
subsequent digit entry to tone mode. When the chips are in tone mode, switch-
ing to the pulse mode will also be recognized.
Rev. 1.20
3 September 30, 2002

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HT9302 Series
Pin Name
DTMF
HDI
HDO
HFI
HFO
LOCK
DOUT
CLOCK
VDD
VSS
I/O
Internal
Connection
Description
This pin is active only when the chip transmits tone dialing signals. Otherwise, it
O CMOS OUT always outputs a low. The pin outputs tone signals to drive the external trans-
mitter amplifier circuit. The load resistor should not be less than 5kW.
This pin is a Schmitt trigger input structure. Active low. Applying a negative go-
I
CMOS IN
Pull-high
ing pulse to this pin can toggle the HDO output once.
An external RC network is recommended for input debouncing. The Pull-high
resistance is 200kW typ.
The HDO is a CMOS output structure. Its output is toggle- controlled by a nega-
tive transition on HDI. When HDO is toggled high, PO keeps high to hold the
O CMOS OUT line. The hold function can be released by setting HFO high or by an on-off hook
operation or by another HDI input. Refer to the functional description for the
hold-line function.
This pin is a Schmitt trigger input structure. Active high. Applying a positive go-
I
CMOS IN
Pull-low
ing pulse to HFI can toggle the HFO once and hence control the hand-free func-
tion. The Pull-low resistance of HFI is 200kW typ.
An external RC network is recommended for input debouncing.
The HFO is a CMOS output structure. Its output is toggle- controlled by a posi-
tive transition on HFI pin. When HFO is high, the hand-free function is enabled
O
CMOS OUT
and PO outputs a high to connect the line.
The hand-free function can be released by setting HDO high or by an on-off-hook
operation or by another HFI input. Refer to the functional description for the
hand-free functional operation.
This is a three-state input/output pin, used for controlling long distance call
function with a lock-switch.
I/O CMOS IN/OUT LOCK=OPEN: Normal dialing (no lock)
LOCK=VDD: ²0, 9² is inhibited for use as the first key input
LOCK=VSS: ²0² is inhibited for use as the first key input
NMOS open drain output pin. It outputs the BCD code of the dialing digits to the
O NMOS OUT LCD driver chip (HT16XX series) or MCU for dialing number display. Refer to
the functional description for the detailed timing.
O
NMOS OUT
NMOS open drain output. When dialing, it outputs a series of pulse trains for
DOUT data synchronization. DOUT data is valid at the falling edge of clock.
¾ ¾ Positive power supply, 2.0V~5.5V for normal operation
¾ ¾ Negative power supply, ground
Approximate internal connection circuits
C M O S IN /O U T
V DD
NM OS OUT
C M O S IN
CM OS OUT
V DD
C M O S IN
P u ll- h ig h
V DD
C M O S IN
P u ll- lo w
O S C IL L A T O R
X1
X2
10M W
20p. 10p.
Rev. 1.20
4 September 30, 2002

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HT9302 Series
Absolute Maximum Ratings
Supply Voltage ...........................................-0.3V to 6V
Input Voltage .............................. VSS-0.3 to VDD+0.3V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Electrical Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
VDD Operating Voltage
¾¾
IDD Operating Current
Pulse Off-hook
2.5V
Keypad entry
Tone No load
ISTB Standby Current
1V
On-hook, no load
No entry
VR Memory Retention Voltage
¾
¾
IR Memory Retention Current
1V On-hook
VIL Input Low Voltage
¾¾
VIH Input High Voltage
¾¾
IXMO
XMUTE Leakage Current
¾
VXMUTE=12V
No entry
IOLXM XMUTE Sink Current
2.5V VXMUTE=0.5V
IHKS HKS Pin Input Current
2.5V VHKS=2.5V
RHFI
HFI Pull-low Resistance
2.5V VHFI=2.5V
RHDI
HDI Pull-high Resistance
2.5V VHDI=0V
IOH1 Keypad Pin Source Current
2.5V VOH=0V
IOL1 Keypad Pin Sink Current
2.5V VOL=2.5V
IOH2 HFO Pin Source Current
2.5V VOH=2V
IOL2 HFO Pin Sink Current
2.5V VOL=0.5V
IOH3 HDO Pin Source Current
2.5V VOH=2V
IOL3 HDO Pin Sink Current
2.5V VOL=0.5V
tFP Pause Time After Flash
Control key
¾
Digit key
tRP
One-key Redialing Pause Time
¾ One-key redialing
tDB Key-in Debounce Time
¾¾
tBRK Break Time for One-key Redialing ¾ One-key redialing
fOSC
System Frequency
¾ Crystal=3.5795MHz
fOSC=3.5795MHz, Ta=25°C
Min. Typ. Max. Unit
2 ¾ 5.5 V
¾ 0.2 1 mA
¾ 0.6 2 mA
¾ ¾ 1 mA
1 ¾ 5.5 V
¾ 0.1 0.2 mA
VSS ¾ 0.2VDD V
0.8VDD ¾
VDD
V
¾ ¾ 1 mA
1 ¾ ¾ mA
¾ ¾ 0.1 mA
¾ 200 ¾ kW
¾ 200 ¾ kW
-4 ¾ 40 mA
200 400
¾ mA
-1 ¾ ¾ mA
1 ¾ ¾ mA
-1 ¾ ¾ mA
1 ¾ ¾ mA
¾ 0.2 ¾
s
¾ 1¾
¾ 1 ¾s
¾ 20 ¾ ms
¾ 1.2 ¾ s
3.5759 3.5795 3.5831 MHz
Rev. 1.20
5 September 30, 2002