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HT9315 Series
15-Memory Tone/Pulse Dialer
Features
Patent Number: 64097, 86474, 113235(R.O.C.), 5424740(U.S.A.)
· Universal specification
· Operating voltage: 2.0V~5.5V
· Low standby current
· Low memory retention current: 0.1mA (Typ.)
· Tone/pulse switchable
· Interface with LCD driver
· 32 digits for redialing
· 32 digits for the SA memory dialing
· One-key redialing
· Pause and P®T key for PBX
· 4´5 keyboard matrix
· 3.58MHz crystal or ceramic resonator
· Hand-free control
· Hold-line control
· Pause, P®T can be saved for redialing
· Lock function
· Keytone function
· Resistor options:
- M/B ratio
- Flash function and flash time (86ms~600ms)
- Pause and P®T duration
- Pulse number
- Keyboard operated IDD lock function
- Keyboard form
· HT9315A/HT9315AL: 18-pin DIP package
HT9315B/HT9315BL: 22-pin SKDIP package
HT9315C/HT9315CL: 20-pin DIP package
HT9315D/HT9315DL: 24-pin SKDIP package
General Description
The HT9315 series tone/pulse dialers are CMOS LSIs for
telecommunication systems. They are designed to meet
various dialing specifications through resistor option ma-
trix.
The HT9315 series are offered in two different ver-
sions. They are HT9315x normal version and
HT9315xL lock version, with keyboard-operated IDD
lock function. The two versions also supply the follow-
ing functions: Hold-line, Hand-free and LCD dialing
number display interface, all of which are suitable for
feature phone applications.
Selection Table
Function
Lock
Item
Function
Hold-Line Hand-Free
LCD
Interface
HT9315x
(Normal version)
HT9315A ¾ ¾ ¾ ¾
HT9315B
¾
Ö
Ö¾
HT9315C ¾ ¾ ¾
Ö
HT9315D
¾
Ö
Ö
Ö
HT9315xL
(Mechanical and Keyboard Operated Lock Version)
HT9315AL
Lock 0
¾¾¾
HT9315BL
Lock 0, 9
Ö
Ö¾
Lock All
HT9315CL
Keyboard
¾
¾
Ö
HT9315DL
Operated Lock
Ö
Ö
Ö
Min.
Flash Time
Package
98ms
18 DIP
22 SKDIP
20 DIP
24 SKDIP
98ms
18 DIP
22 SKDIP
20 DIP
24 SKDIP
Rev. 1.20
1 October 1, 2002

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Block Diagram
HT9315 Series
C1
K ey
C o lu m n
C5
R1
K ey R ow
R4
X1
D iv id e r
X2
.SM
K ey
. u n c tio n
E ncoder
E ncoder
D ebounce
C lo c k
G e n e ra to r
C o n tro l
W RM
C o u n te r
SRAM
ADDRL
C heck
Tone
E ncoder
C o n v e rte r
Tone
O ut
P u ls e
O ut
. la s h
M o d e In
H D /H .
M /B T im e r
K e y to n e
G e n e ra to r
DOUT
C LO C K
D TM .
PO
XM U TE
HKS
H .I
HDI
HDO
H .O
M ODE
Pin Assignment
HT9315x/xL version
C1
C2
C3
C4
C5
X1
X2
XM U TE
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
H T 9 3 1 5 A /A L
1 8 D IP -A
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
HDI
C1
C2
C3
C4
C5
X1
X2
XM U TE
VSS
H .I
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
H T 9 3 1 5 B /B L
2 2 S K D IP -A
HDO
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
H .O
C1
C2
C3
C4
C5
X1
X2
XM U TE
VSS
DOUT
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
H T 9 3 1 5 C /C L
2 0 D IP -A
R4
R3
R2
R1
M ODE
D TM .
PO
HKS
VDD
C LO C K
HDI
C1
C2
C3
C4
C5
X1
X2
XM U TE
VSS
H .I
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
24 H D O
23 R 4
22 R 3
21 R 2
20 R 1
19 M O D E
18 D TM .
17 P O
16 H K S
15 V D D
14 H .O
13 C LO C K
H T 9 3 1 5 D /D L
2 4 S K D IP -A
Keyboard Information
. o rm A
C1 C2 C3 C4 C5
R1 1
R2 4
R3 7
R 4 * /T
2
5
8
0
3 SA EM 1
6 . EM 2
9 A EM 3
# R /P S T
. o rm B
C1 C2 C3 C4 C5
R1 1 2 3 P EM 1
R2 4 5 6 . EM 2
R3 7 8 9 A EM 3
R 4 * /T
0
#
R ST
Rev. 1.20
2 October 1, 2002

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HT9315 Series
Pin Description
Pin Name
I/O
Internal
Connection
Description
C1~C5
R1~R4
I/O
CMOS
IN/OUT
These pins form a 4´5 keyboard matrix which can perform keyboard input detection
and dialing specification setting functions. When on-hook (HKS=high) all the pins are
set high. While off-hook the column group (C1~C5) remains low and the row group
(R1~R4) is set high for key input detection.
An inexpensive single contact 4´5 keyboard can be used as an input device.
Pressing a key connects a single column to a single row, and actuates the system os-
cillator that results in a dialing signal output. If more than two keys are pressed at the
same time, no response occurs. The key-in debounce time is 20ms. Refer to the key-
board information for keyboard arrangement and to the functional description for dial-
ing specification selection.
X1 I
The system oscillator consists of an inverter, a bias resistor and the necessary
load capacitor on chip. Connecting a standard 3.579545MHz crystal or ceramic
OSCILLATOR resonator to the X1 and X2 terminals can implement the oscillator function. The
X2 O
oscillator is turned off in the standby mode, and is actuated whenever a keyboard
entry is detected.
XMUTE is an NMOS open drain structure pulled to VSS during dialing signal
XMUTE O NMOS OUT transmission. Otherwise, it is an open circuit. XMUTE is used to mute the speech
circuit when transmitting the dial signal.
HKS
This pin is used to monitor the status of the hook-switch and its combination with
HFI/HDI can control the PO pin output to make or break the line.
I
CMOS IN
HKS=VDD: On-hook state (PO=low). Except for HFI/HDI
(hand-free/hold-line control input), other functions are all disabled.
HKS=VSS: Off-hook state (PO=high). The chip is in the standby mode and ready to
receive the key input.
This pin is a CMOS output structure which by receiving the HKS and HFO/HDO
signals, control the dialer to connect or disconnect the telephone line.
PO outputs a low to break line when HKS is high (on-hook) and HFO/HDO is low.
PO O CMOS OUT PO outputs a high to make line when HKS is low (off-hook) or HFO is high or HDO
is high.
During the off-hook state, this pin also outputs the dialing pulse train in pulse
mode dialing. While in the tone mode, this pin is always high.
MODE I/O
CMOS
IN/OUT
This is a three-state input/output pin, use for dialing mode selection, either Tone
mode or Pulse mode, 10pps/20pps
MODE=VDD: Pulse mode, 10pps
MODE=OPEN: Pulse mode, 20pps
MODE=VSS: Tone mode
During the pulse mode dialing, switching this pin to the tone mode changes the
subsequent digit entry to tone mode. When the chips are in tone mode, switching
to pulse mode will also be recognized.
DTMF
This pin is active only when the chip transmits tone dialing signals. Otherwise, it
O CMOS OUT always outputs a low. The pin outputs tone signals to drive the external transmitter
amplifier circuit. The load resistor should not be less than 5kW.
This pin is a Schmitt trigger input structure. Active low. Applying a negative going
HDI
I
CMOS IN pulse to this pin can toggle the HDO output once.
Pull-High An external RC network is recommended for input debouncing. The pull-high re-
sistance is 200kW typ.
HDO
The HDO is a CMOS output structure. Its output is toggle- controlled by a negative
transition on HDI. When HDO is toggled high, PO keeps high to hold the line. The
O CMOS OUT hold function can be released by setting HFO high or by an on/off hook operation
or by another HDI input. Refer to the functional description for the hold-line func-
tion.
Rev. 1.20
3 October 1, 2002

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HT9315 Series
Pin Name
I/O
Internal
Connection
Description
This pin is a Schmitt trigger input structure. Active high. Applying a positive pulse
HFI
I
CMOS IN to HFI can toggle the HFO once and hence control the hand-free function. The
Pull-Low pull-low resistance of HFI is 200kW typ.
An external RC network is recommended for input debouncing.
HFO
The HFO is a CMOS output structure. Its output is toggle- controlled by a positive
transition on HFI pin. When HFO is high, the hand-free function is enabled and PO
O
CMOS OUT
outputs a high to connect the line.
The hand-free function can be released by setting HDO high or by an on-off-hook op-
eration or by another HFI input. Refer to the functional description for the hand-free
functional operation.
DOUT
NMOS open drain output pin. It outputs the BCD code of the dialing digits to the
O NMOS OUT LCD driver chip (HT16XX series) or MCU for dialing number display. Refer to the
functional description for the detailed timing.
CLOCK
O
NMOS OUT
NMOS open drain output. When dialing, it outputs a series of pulse trains for
DOUT data synchronization. DOUT data is valid at the falling edge of the clock.
VDD
¾
¾ Positive power supply, 2.0V~5.5V for normal operation
VSS
¾
¾ Negative power supply, ground
Approximate internal connection circuits
C M O S IN /O U T
VDD
NM OS OUT
C M O S IN
CM OS OUT
VDD
C M O S IN
P u ll- H ig h
C M O S IN
P u ll- L o w
O S C IL L A T O R
X1 X2
20P 10M
10P
EN
Absolute Maximum Ratings
Supply Voltage ...........................................-0.3V to 6V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................. VSS-0.3 to VDD+0.3V
Operating Temperature ..........................-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.20
4 October 1, 2002

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HT9315 Series
Electrical Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
VDD Operating Voltage
¾¾
IDD Operating Current
Pulse Off-hook
2.5V
Keypad entry
Tone No load
ISTB Standby Current
1V
On-hook, no load
No entry
VR Memory Retention Voltage
¾
¾
IR Memory Retention Current
1V On-hook
VIL Input Low Voltage
¾¾
VIH Input High Voltage
¾¾
IXMO XMUTE Leakage Current
¾ VXMUTE=12V, No entry
IOLXM XMUTE Sink Current
2.5V VXMUTE=0.5V
IHKS HKS Pin Input Current
2.5V VHKS=2.5V
RHFI HFI Pull-Low Resistance
2.5V VHFI=2.5V
RHDI HDI Pull-High Resistance
2.5V VHDI=0V
IOH1 Keypad Pin Source Current
2.5V VOH=0V
IOL1 Keypad Pin Sink Current
2.5V VOL=2.5V
IOH2 HFO Pin Source Current
2.5V VOH=2V
IOL2 HFO Pin Sink Current
2.5V VOL=0.5V
IOH3 HDO Pin Source Current
2.5V VOH=2V
IOL3 HDO Pin Sink Current
2.5V VOL=0.5V
TFP Pause Time After Flash
Control key
¾
Digit key
TRP One-key Redialing Pause Time
¾ One-key redialing
TDB Key-in Debounce Time ¾ ¾
TBRK Break Time for One-key Redialing ¾ One-key redialing
FOSC System Frequency
¾ Crystal=3.5795MHz
FOSC=3.5795MHz, Ta=25°C
Min. Typ. Max. Unit
2 ¾ 5.5 V
¾ 0.2 1 mA
¾ 0.6 2 mA
¾ ¾ 1 mA
1 5.5 V
¾ 0.1 0.2 mA
VSS ¾ 0.2VDD V
0.8VDD ¾ VDD V
¾ ¾ 1 mA
1 ¾ ¾ mA
¾ ¾ 0.1 mA
¾ 200 ¾ kW
¾ 200 ¾ kW
-4 ¾ -40 mA
200 400 ¾ mA
-1 ¾ ¾ mA
1 ¾ ¾ mA
-1 ¾ ¾ mA
1 ¾ ¾ mA
¾ 0.2 ¾
s
¾ 1¾
¾ 1 ¾s
¾ 20 ¾ ms
¾ 1.2 ¾ s
3.5759 3.5795 3.5831 MHz
Rev. 1.20
5 October 1, 2002