HS9-82C37ARH-8.pdf 데이터시트 (총 29 페이지) - 파일 다운로드 HS9-82C37ARH-8 데이타시트 다운로드

No Preview Available !

HS-82C37ARH
August 1995
Radiation Hardened CMOS High
Performance Programmable DMA Controller
Features
Description
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset > 108 RAD (Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB = 50µA Maximum
- IDDOP = 4.0mA/MHz Maximum
• Pin Compatible with NMOS 8237A and the Intersil
82C37A
The Intersil HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Intersil hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.
• High Speed Data Transfers Up To 2.5 MBPS With 5MHz
Clock
• Four Independent Maskable Channels With Autoinitializa-
tion Capability
• Expandable to Any Number of Channels
• Memory-to-Memory Transfer Capability
• CMOS Compatible
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either
hardware or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Intersil hardened field CMOS process results in
performance equal to or greater than existing radiation resis-
tant products at a fraction of the power.
Ordering Information
PART NUMBER
HS1-82C37ARH-Q
HS1-82C37ARH-8
HS1-82C37ARH-Sample
HS9-82C37ARH-Q
HS9-82C37ARH-8
HS9-82C37ARH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
+25oC
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
918
Spec Number 518058
File Number 3042.1

No Preview Available !

HS-82C37ARH
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T40
TOP VIEW
IOR 1
IOW 2
MEMR 3
MEMW 4
NC 5
READY 6
HLDA 7
ADSTB 8
AEN 9
HRQ 10
CS 11
CLK 12
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) 20
VSS
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VDD
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) INTERSIL OUTLINE K42.A
TOP VIEW
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
NC
DREQ3
DREQ2
DREQ1
DREQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 A7
41 A6
40 A5
39 A4
38 EOP
37 A3
36 A2
35 A1
34 A0
33 VDD
32 DB0
31 DB1
30 DB2
29 DB3
28 DB4
27 NC
26 DACK0
25 DACK1
24 DB5
23 DB6
22 DB7
Functional Diagram
EOP
RESET
CS
READY
CLOCK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0-
DREQ3
HLDA
HDQ
DACK0-
DACK3
4
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG (16)
16 BIT BUS
READ BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
INC DECREMENTOR
TEMP ADDRESS
REG (16)
16 BIT BUS
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
I/O BUFFER
A0-A3
OUTPUT
BUFFER
A4-A7
COMMAND
CONTROL
COMMAND (8)
MASK (4)
REQUEST (4)
WRITE
BUFFER
READ
BUFFER
INTERNAL DATA BUS
D0-D1
I/O BUFFER
DB0-DB7
MODE
(4 x 6)
STATUS (8)
TEMPORARY
(8)
Spec Number 518058
919

No Preview Available !

HS-82C37ARH
Pin Descriptions
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
VDD
31
VDD: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for de-
coupling.
GND
20
Ground
CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control HS-82C37ARH
operations. This input may be driven from DC to 5MHz and may be stopped in either high or low state
for standby operation.
CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
13
I RESET: This is an active high input which clears the Command, Status, Request and Temporary Reg-
isters, the First/Last Flip-Flop, and the Mode Register Counter. The Mask Register is Set to ignore re-
quests. Following a Reset, the controller is in an idle cycle.
READY
6
I READY: This signal can be sued to extend the memory read and write pulses from the HS-82C37ARH
to accommodate slow memories or I/O devices. Ready must not make transitions during its specified
set-up and hold times. Ready is ignored in Verify Transfer mode.
HLDA
7
I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that is has relin-
quished control of the system busses.
DREQ0-
DREQ3
16-19
I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs
used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and
DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK
will acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes
these lines to active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs
should be pulled High or Low (inactive) and the corresponding mask bit set.
DB0-
DB7
21-23
26-30
I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus.
The outputs are enabled in the Program Condition during the I/O Read to output the contents of a reg-
ister to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the
CPU is programming the HS-82C37ARH Control Registers. During DMA cycles, the most significant 8
bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In Mem-
ory-to-Memory operations, data from the memory enters the HS-82C37ARH on the data bus during the
read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the
data into the new memory location.
IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to read the internal registers. In the Active cycle, it is an output control signal
used by the HS-82C37ARH to access data from a peripheral during a DMA Write transfer.
IOW
2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to load information into the HS-82C37ARH. In the Active cycle, it is an output
control signal used by the HS-82C37ARH to load data to the peripheral during a DMA Read transfer.
EOP
36 I/O END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning
the completion of DMA services is available at the bidirectional EOP pin.
The HS-82C37ARH allows an external signal to terminate an active DMA service by pulling the EOP
pin low. A pulse is generated by the HS-82C37ARH when terminal count (TC) for any channel is
reached, except for channel 0 in Memory-to-Memory mode. During Memory-to-Memory transfers, EOP
will be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor.
When an EOP pulse occurs, whether internally or externally generated, the HS-82C37ARH will termi-
nate the service, and if Autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the Status Register will be set for the currently active channel
by EOP unless the channel is programmed for Autoinitialize. In that case, the mask bit remains clear.
A0-A3
32-35
I/O Address: The four least significant address lines are bidirectional three-state signals. In the Idle cycle,
they are inputs and are used by the HS-80C86RH to address the internal registers to be loaded or read.
In the Active cycle, they are outputs and provide the lower 4 bits of the output address.
Spec Number 518058
920

No Preview Available !

HS-82C37ARH
Pin Descriptions (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
A4-A7
37-40
O Address: The four most significant address lines are three-state outputs and provide 4 bits of address.
These lines are enabled only during the Active cycle.
HRQ 10 O Hold Request: The Hold Request (HRQ) output is used to request control of the system bus. When a
DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the HS-
82C37ARH issues HRQ. The HLDA signal then informs the controller when access to the system bus-
ses is permitted. For stand-alone operation where the HS-82C37ARH always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
DACK0- 14,15, 24,
DACK3
25
O DMA Acknowledge: DMA acknowledge is used to notify the individual peripherals when one has been
granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.
AEN 9 O Address Enable: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the
system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
AEN is active HIGH.
ADSTB
8
O Address Strobe: This is an active high signal used to control latching of the upper address byte. It will
drive directly the strobe input of external transparent octal latches, such as the 82C82. During block op-
erations, ADSTB will only be issued when the upper address byte must be updated, thus speeding op-
eration through elimination of S1 states. (See Note 2).
MEMR
3
O Memory Read: The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a Memory-to-Memory transfer.
MEMW
4
O Memory Write: The Memory Write is an active low three-state output used to write data to the selected
memory location during a DMA Write or a Memory-to-Memory transfer.
NC 5
No connect. Pin 5 is open and should not be tested for continuity.
Spec Number 518058
921

No Preview Available !

Specifications HS-82C37ARH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Input or Output Voltage Applied . . . . . . . .VSS - 0.3V to VDD + 0.3V
for All Grades
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Typical Derating Factor. . . . . . . . . . . . 4mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
SBDIP Package. . . . . . . . . . . . . . . . . . . . 38oC/W
θJC
5oC/W
Ceramic Flatpack Package . . . . . . . . . . . 72oC/W 10oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.3mW/C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.9mW/C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -1.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
TTL Output High Voltage
CMOS Output High Volt-
age
Output Low Voltage
Input Leakage Current
Output Leakage Current
Standby Power Supply
Current
Operating Power Supply
Current
Functional Tests
Noise Immunity Functional
Test
SYMBOL
VOH1
VOH2
VOL1
IIL or IIH
IOZL or
IOZH
IDDSB
IDDOP
FT
FN
CONDITIONS
GROUP A
SUBGROUP
VDD = 4.5V, IO = -2.5mA,
VIN = 0V or 4.0V
1, 2, 3
VDD = 4.5V, IO = -100µA,
VIN = 0V or 4.0V
1, 2, 3
VDD = 4.5V, IO = +2.5mA,
VIN = 0V or 4.0V
1, 2, 3
VDD = 5.5V, VIN = 0V or
5.5V Pins: 6, 7, 11-13, 16-19
1, 2, 3
VDD = 5.5V, VIN = 0V or
5.5V Pins: 1-4, 21-23, 26-
30, 32-40
1, 2, 3
VDD = 5.5V, IO = 0mA,
VIN = GND or VDD
1, 2, 3
VDD = 5.5V, IO = 0mA,
VIN = GND or VDD,
f = 5MHz
1, 2, 3
VDD = 4.5V and 5.5V,
VIN = GND or VDD,
f = 1MHz
7, 8A, 8B
VDD = 4.5V and 5.5V, VIN =
GND or VDD - 1.5V and
VDD = 4.5V, VIN = 0.8V or
VDD
7, 8A, 8B
LIMITS
TEMPERATURE MIN MAX UNITS
+25oC, +125oC,
-55oC
3.0
-
V
+25oC, +125oC, VDD-
-55oC
0.4
-
V
+25oC, +125oC,
-55oC
-
0.4
V
+25oC, +125oC,
-55oC
-1.0
1.0
µA
+25oC, +125oC,
-55oC
-10
10
µA
+25oC, +125oC, - +50 µA
-55oC
+25oC, +125oC,
-55oC
-
20 mA
+25oC, +125oC,
-55oC
-
-
-
+25oC, +125oC,
-55oC
-
-
-
Spec Number 518058
922