CXK5T81000AM-10LLX.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 CXK5T81000AM-10LLX 데이타시트 다운로드

No Preview Available !

CXK5T81000ATM/AYM/AM -10LLX/12LLX
131072-word × 8-bit High Speed CMOS Static RAM Preliminary
For the availability of this product, please contact the sales office.
Description
The CXK5T81000ATM/AYM/AM is a high speed
CMOS static RAM organized as 131072-words by
8-bits.
Special feature are low power consumption and
high speed.
The CXK5T81000ATM/AYM/AM is a suitable RAM
for portable equipment with battery back up.
CXK5T81000ATM
32 pin TSOP (Plastic)
CXK5T81000AYM
32 pin TSOP (Plastic)
Features
Extended operating temperature range:
–25 to +85°C
Wide supply voltage range operation: 2.7 to 3.6V
Fast access time:
(Access time)
3.0V operation -10LLX 100ns (Max.)
-12LLX 120ns (Max.)
3.3V operation -10LLX 85ns (Max.)
-12LLX 100ns (Max.)
Low standby current:
28µA (Max.)
Low data retention current: 24µA (Max.)
Low voltage data retention: 2.0V (Min.)
Package line-up
CXK5T81000ATM/AYM
8mm × 20mm 32 pin TSOP package
CXK5T81000AM
525mil 32 pin SOP package
Function
131072-word × 8-bit static RAM
Structure
Silicon gate CMOS IC
CXK5T81000AM
32 pin SOP (Plastic)
Block Diagram
A10
A11
A9
A8
A13
A15
Buffer
A16
A14
A12
A7
Row
Decoder
Memory
Matrix
1024 × 1024
A6
A5
A4
A3
A2
A1
A0
OE
WE
CE1
CE2
Buffer
Buffer
I/O Gate
Column
Decoder
I/O Buffer
I/O1 I/O8
VCC
GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96324-ST

No Preview Available !

CXK5T81000ATM/AYM/AM
Pin Configuration (Top View)
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
CXK5T81000ATM
(Standard Pinout)
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
NC 9
VCC 8
A15 7
CE2 6
WE 5
A13 4
A8 3
A9 2
A11 1
CXK5T81000AYM
(Mirror Image Pinout)
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
17 A3
18 A2
19 A1
20 A0
21 I/O1
22 I/O2
23 I/O3
24 GND
25 I/O4
26 I/O5
27 I/O6
28 I/O7
29 I/O8
30 CE1
31 A10
32 OE
Pin Description
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
GND 16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
Symbol
A0 to A16
I/O1 to I/O8
CE1, CE2
WE
OE
VCC
GND
NC
Description
Address input
Data input output
Chip enable 1, 2 input
Write enable input
Output enable input
Power supply
Ground
No connection
CXK5T81000AM
Absolute Maximum Ratings
(Ta = 25°C, GND = 0V)
Item
Supply voltage
Input voltage
Input and output voltage
Symbol
Rating
VCC –0.5 to +4.6
VIN –0.51 to VCC + 0.5
VI/O –0.51 to VCC + 0.5
Unit
V
V
V
Allowable power dissipation
Operating temperature
PD
Topr
0.7
–25 to +85
W
°C
Storage temperature
Tstg
–55 to +150
°C
Soldering temperature · time Tsolder
235 · 10
1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns.
°C · s
Truth Table
CE1 CE2 OE WE
Mode
H × × × Not selected
× L × × Not selected
L H H H Output disable
L H L H Read
L H × L Write
× : “H” or “L”
I/O pin
High Z
High Z
High Z
Data out
Data in
VCC Current
ISB1, ISB2
ISB1, ISB2
ICC1, ICC2, ICC3
ICC1, ICC2, ICC3
ICC1, ICC2, ICC3
–2–

No Preview Available !

CXK5T81000ATM/AYM/AM
DC Recommended Operating Conditions
Item
Symbol
VCC = 2.7 to 3.6V
Min. Typ. Max.
Supply voltage
VCC 2.7 3.3
Input high voltage
VIH
2.4 —
Input low voltage
VIL
–0.31
1 VIL = –3.0V Min. for pulse width less than 50ns.
3.6
VCC + 0.3
0.4
(Ta = –25 to +85°C, GND = 0V)
VCC = 3.3V ± 0.3V
Min. Typ. Max.
Unit
3.0 3.3 3.6
2.2
–0.31
— VCC + 0.3 V
— 0.6
Electrical Characteristics
• DC Characteristics
Item
Symbol
(VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C)
Test conditions
Min. Typ.1 Max. Unit
Input leakage current ILI VIN = GND to VCC
–1 — +1 µA
Output leakage current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
–1 — +1 µA
Operating power supply
current
ICC1
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
Min. cycle
ICC2 duty = 100%
IOUT = 0mA
10LLX
12LLX
—1
3 mA
— 252 353
mA
— 25 35
Average operating current
ICC3
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 0.2V
CE2 Vcc – 0.2V
VIL 0.2V
VIH Vcc – 0.2V
— 5 10 mA
Standby current
CE2 0.2V
–25 to +85°C — — 28
{ISB1
or
CE1 Vcc – 0.2V –25 to +70°C
CE2 Vcc – 0.2V +25°C
0.48
14 µA
ISB2 CE1 = VIH or CE2 = VIL
— 0.12 1.4 mA
Output high voltage
VOH IOH = –2.0mA
2.4 —
—V
Output low voltage
VOL IOL = 2.0mA
1 VCC = 3.3V, Ta = 25°C
2 ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V)
3 ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V)
— — 0.4 V
–3–

No Preview Available !

CXK5T81000ATM/AYM/AM
I/O capacitance
Item Symbol Test conditions Min.
Input capacitance
CIN VIN = 0V
I/O capacitance
CI/O
VI/O = 0V
Note) This parameter is sampled and is not 100% tested.
(Ta = 25°C, f = 1MHz)
Typ. Max. Unit
— 8 pF
— 10 pF
AC Characteristics
• AC test conditions
(Ta = –25 to +85°C)
Item
Input pulse high level
Conditions
VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V
VIH = 2.4V
VIH = 2.2V
Input pulse low level
Input rise time
Input fall time
VIL = 0.4V
tr = 5ns
tf = 5ns
VIL = 0.6V
tr = 5ns
tf = 5ns
Input and output reference level
-10LLX
Output load conditions
-12LLX
1.4V
1.4V
CL1 = 100pF, 1TTL CL1 = 30pF, 1TTL
CL1 = 100pF, 1TTL CL1 = 100pF, 1TTL
1 CL includes scope and jig capacitances.
Test circuit
TTL
CL
–4–

No Preview Available !

CXK5T81000ATM/AYM/AM
• Read cycle (WE = “H”)
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
Item
Symbol -10LLX
-12LLX
-10LLX
-12LLX Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read cycle time
tRC 100 — 120 — 85 — 100 — ns
Address access time
tAA — 100 — 120 — 85 — 100 ns
Chip enable access time (CE1)
tCO1 — 100 — 120 — 85 — 100 ns
Chip enable access time (CE2)
tCO2 — 100 — 120 — 85 — 100 ns
Output enable to output valid
tOE — 50 — 60 — 40 — 50 ns
Output hold from address change
tOH 10 — 10 — 10 — 10 — ns
Chip enable to output in low Z
(CE1, CE2)
tLZ1
tLZ2
10 — 10 — 10 — 10 — ns
Output enable to output in low Z (OE) tOLZ
5 — 5 — 5 — 5 — ns
Chip disable to output in high Z
(CE1, CE2)
tHZ11
tHZ21
40
40
35
40 ns
Output disable to output in high Z (OE) tOHZ1 — 35 — 35 — 30 — 35 ns
1 tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
Item
Symbol -10LLX
-12LLX
-10LLX
-12LLX Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Write cycle time
tWC 100 — 120 — 85 — 100 — ns
Address valid to end of write
tAW 80 — 100 — 70 — 80 — ns
Chip enable to end of write
tCW 80 — 100 — 70 — 80 — ns
Data to write time overlap
tDW 40 — 50 — 35 — 40 — ns
Data hold from write time
tDH 0 — 0 — 0 — 0 — ns
Write pulse width
tWP 70 — 70 — 60 — 70 — ns
Address setup time
tAS 0 — 0 — 0 — 0 — ns
Write recovery time (WE)
tWR 0 — 0 — 0 — 0 — ns
Write recovery time (CE1, CE2)
tWR1
0 — 0 — 0 — 0 — ns
Output active from end of write
Write to output in high Z
tOW 5 — 5 — 5 — 5 — ns
tWHZ2 — 40 — 40 — 35 — 40 ns
2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–