The HEF4042B is a 4-bit latch with four data inputs (D0 to
D3), four buffered latch outputs (O0 to O3), four buffered
complementary latch outputs (O0 to O3) and two common
enable inputs (E0 and E1). Information on D0 to D3 is
transferred to O0 to O3 while both E0 and E1 are in the
same state, either HIGH or LOW. O0 to O3 follow D0 to
D3 as long as both E0 and E1 remain in the same state.
When E0 and E1 are different, D0 to D3 do not affect O0 to
O3 and the information in the latch is stored.
O0 to O3 are always the complement of O0 to O3. The
exclusive-OR input structure allows the choice of either
polarity for E0 and E1. With one enable input HIGH, the
other enable input is active HIGH; with one enable input
LOW, the other enable input is active LOW.
Fig.2 Pinning diagram.
HEF4042BP(N): 16-lead DIL; plastic
HEF4042BD(F): 16-lead DIL; ceramic (cerdip)
HEF4042BT(D): 16-lead SO; plastic
( ): Package Designator North America
D0 to D3
E0 and E1
O0 to O3
O0 to O3
parallel latch outputs
complementary parallel latch outputs
Some examples of applications for the HEF4042B are:
• Buffer storage
• Holding register
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.