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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4066B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995

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Philips Semiconductors
Quadruple bilateral switches
Product specification
HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to VDD a low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to VSS the switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
E0 to E3
Y0 to Y3
Z0 to Z3
enable inputs
input/output terminals
input/output terminals
APPLICATION INFORMATION
An example of application for the HEF4066B is:
Analogue and digital switching
January 1995
Fig.3 Schematic diagram (one switch).
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Philips Semiconductors
Quadruple bilateral switches
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch
For other RATINGS see Family Specifications
DC CHARACTERISTICS
Tamb = 25 °C
ON resistance
ON resistance
ON resistance
’ ON resistance
between any two
channels
OFF state leakage
current, any
channel OFF
En input voltage
LOW
VDD
V
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
SYMBOL MIN. TYP. MAX.
350 2500
RON 80 245
60 175
115 340
RON 50 160
40 115
120 365
RON 65 200
50 155
25 − Ω
RON
10 − Ω
5−Ω
− − − nA
IOZ − − − nA
− − 200 nA
2,25 1 V
VIL 4,50 2 V
6,75 2 V
Product specification
HEF4066B
gates
P max. 100 mW
CONDITIONS
En at VDD
Vis = VSS to VDD
see Fig.4
En at VDD
Vis = VSS
see Fig.4
En at VDD
Vis = VDD
see Fig.4
En at VDD
Vis = VSS to VDD
see Fig.4
En at VSS
Iis = 10 µA
see Fig.9
Quiescent device
current
Input leakage current at En
VDD SYMBOL
Tamb (°c)
V 40 +25 +85
MAX. MAX. MAX.
5
10 IDD
15
15 ± IIN
1,0 1,0 7,5 µA
2,0 2,0 15,0 µA
4,0 4,0 30,0 µA
300 1000 nA
CONDITIONS
VSS = 0; all valid
input combinations;
VI = VSS or VDD
En at VSS or VDD
January 1995
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