4093B.pdf 데이터시트 (총 6 페이지) - 파일 다운로드 4093B 데이타시트 다운로드

No Preview Available !

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4093B
gates
Quadruple 2-input NAND Schmitt
trigger
Product specification
File under Integrated Circuits, IC04
January 1995

No Preview Available !

Philips Semiconductors
Quadruple 2-input NAND Schmitt trigger
DESCRIPTION
The HEF4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a two-input NAND gate with
Schmitt-trigger action on both inputs. The gate switches at
different points for positive and negative-going signals.
The difference between the positive voltage (VP) and the
negative voltage (VN) is defined as hysteresis voltage
(VH).
Product specification
HEF4093B
gates
Fig.2 Pinning diagram.
HEF4093BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4093BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4093BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2

No Preview Available !

Philips Semiconductors
Quadruple 2-input NAND Schmitt trigger
Product specification
HEF4093B
gates
DC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C
Hysteresis
voltage
Switching levels
positive-going
input voltage
negative-going
input voltage
VDD
V
5
10
15
5
10
15
5
10
15
SYMBOL MIN. TYP. MAX.
0,4 0,7
VH
0,6 1,0
0,7 1,3
1,9 2,9
3,5
VP
3,6 5,2
7
4,7 7,3 11
1,5 2,2
3,1
VN 3 4,2 6,4
4 6,0 10,3
V
V
V
V
V
V
V
V
V
Fig.4 Transfer characteristic.
Fig.5 Waveforms showing definition of
VP, VN and VH; where VN and VP are
between limits of 30% and 70%.
January 1995
3

No Preview Available !

Philips Semiconductors
Quadruple 2-input NAND Schmitt trigger
Product specification
HEF4093B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
90 185 ns
40 80 ns
30 60 ns
85 170 ns
40 80 ns
30 60 ns
60 120 ns
30 60 ns
20 40 ns
60 120 ns
30 60 ns
20 40 ns
TYPICAL EXTRAPOLATION
FORMULA
63 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1300 fi + ∑(foCL) × VDD2
where
10
6400 fi + ∑(foCL) × VDD2
fi = input freq. (MHz)
15
18 700 fi + ∑(foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4

No Preview Available !

Philips Semiconductors
Quadruple 2-input NAND Schmitt trigger
Product specification
HEF4093B
gates
Fig.6 Typical drain current as a function of input
voltage; VDD = 5 V; Tamb = 25 °C.
Fig.7 Typical drain current as a function of input
voltage; VDD =10 V; Tamb = 25 °C.
Fig.8 Typical drain current as a function of input
voltage; VDD = 15 V; Tamb = 25 °C.
January 1995
5