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Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

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Integrated
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Systems, Inc.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4 OP_IN
9 nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
6 nVC
7 VC
Input
External loop filter connections. See Figure 5,
External Loop Filter, on pg. 8.
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12 FOUT1
13 nFOUT1
15 FOUT0
16 nFOUT0
17 INIT
Output
Output
Input
No internal terminator
Clock output pair 1. Differential LVPECL.
No internal terminator
Internal pull-UP resistor1
Clock output pair 0. Differential LVPECL.
Power-on Initialization; LVCMOS/LVTTL:
Logic 1 allows device to enter narrow mode if
selected (in addition must have 8 LOL=0 counts)
Logic 0 forced device into wide bandwidth mode.
18 P_SEL
Internal pull-down1
Post-PLL , P divider selection. LVCMOS/LVTTL.
See Table 4, P Divider Selector Values
and Frequencies, on pg. 3.
20 nDIF_REF1
Biased to Vcc/2 2
Reference Differential LVPECL/ LVDS
Input clock input Differential LVPECL/ LVDS, or single
21 DIF_REF1
Internal pull-down resistor1 pair 1.
ended LVCMOS/ LVTTL
22 REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL.
Logic 1 selects DIF_REF1/nDIF_REF1 inputs
Logic 0 selects DIF_REF0/nDIF_REF0 inputs
23 nDIF_REF0
Biased to Vcc/2 3
Reference Differential LVPECL/ LVDS
24
DIF_REF0
Input clock input Differential LVPECL/ LVDS, or single
Internal pull-down resistor1 pair 0.
ended LVCMOS/ LVTTL
25 AUTO
Automatic/manual reselection mode for clock input:
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
27 MR_SEL2
28 MR_SEL1
29 MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
Input Internal pull-UP resistor1 See Table 3, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Reference Acknowledgement pin for input mux state;
30 REF_ACK Output
outputs the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
31 LOL
Output
Loss of Lock indicator output. 4
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32 NBW
Narrow Bandwidth enable. LVCMOS/LVTTL:
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
Table 2: Pin Descriptions
Note 2: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 10.
Note 3: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF0 as LVCMOS input. See DC Characteristics on pg. 10.
Note 4: See LVCMOS Outputs in DC Characteristics on pg. 10.
M1040 Datasheet Rev 0.1
2 of 12
Revised 11Nov2003
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DETAILED BLOCK DIAGRAM
M1040
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
RLOOP CLOOP
OP_IN
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
RPOST
CPOST
CPOST
nOP_OUT nVC
VC
External
Loop Filter
Components
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R
Divider
PLL
Phase
Detector RIN
R IN
Loop Filter
Amplifier
LOL
Phase
Detector
M Divider
M / R Divider
LUT
P_SEL
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
P Divider
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up is defined in
Table 3.
M1040 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
000
81
8
19.44
19.44
0 0 1 64 8
8
19.44
2.43
010
21
2
77.76
77.76
0 1 1 16 8
2
77.76
9.72
100
11
1
155.52
155.52
101
110
88
1
Test Mode1 N/A
155.52
N/A
19.44
N/A
111
2 8 0.25
622.08
77.76
Table 3: M1040 M/R Divider LUT
Note 1: Factory test mode; do not use.
Table 3 provides example Fin and phase detector
frequencies with 155.52MHz VCSO devices
(e.g., M1040-11-155.5200). See “Ordering Information”
on pg. 12.
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
Post-PLL Divider
The M1040 also features a post-PLL (P) divider for the
output clocks. It divides the VCSO frequency to produce
one of two selectable output frequencies (1/2 or 1/1 of
the VCSO frequency). That selected frequency appears
on both clock output pairs. The P_SEL pin selects the
value for the P divider.
P_SEL
P Value
M1040-11-155.52
Output Frequency
(MHz)
1 2 77.76
0 1 155.52
Table 4: P Divider Selector Values and Frequencies
M1040 Datasheet Rev 0.1
3 of 12
Revised 11Nov2003
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FUNCTIONAL DESCRIPTION
The M1040 is a PLL (Phase Locked Loop) based clock
generator that generates two output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high “Q” SAW delay line provides a low jitter
clock output.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Table 3 on pg. 3. The look-up table provides
flexibility in both the overall frequency multiplication
ratio (total PLL ratio) and phase detector frequency.
External loop filter component values influence the PLL
bandwidth, which is used to optimize jitter attenuation
characteristics.
The device features dual differential inputs with two
input selection modes: manual and automatic upon
clock failure. (The differential inputs are internally
configured for easy single-ended operation.)
The M1040 also includes: a Loss of Lock (LOL) indicator,
a reference mux state acknowledge pin (REF_ACK), a
Narrow Bandwidth control input pin (NBW pin), and a
Power-on Initialization (INIT) input (which overrides
NBW=0 to facilitate acquisition of phase lock).
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1040. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
Hitless Switching (HS) provides a controlled output
clock phase change during a reference clock
reselection. HS is triggered by a Loss of Lock detection
by the PLL.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been facili-
tated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with
50kto Vcc and 50kto ground. Figure 4 shows the
input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
LVCMOS/
LVTTL
LVPECL
VCC
127
82
X
VCC
127
VCC
50k
50k
50k
VCC
50k
50k
MUX
0
1
82
50k
REF_SEL
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127
and 82resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
M1040 Datasheet Rev 0.1
4 of 12
Revised 11Nov2003
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PLL Operation
The M1040 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
Fvcso
=
Fin ×
M---
R
For the available M divider and R divider look-up table
combinations, Tables 3 and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the M1040-11-155.5200.
(See “Ordering Information”, pg. 12.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1040 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 6.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Fout = --F----v---c---s---o---- = Fin × ------M-----------
P R× P
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Loss of Lock Indicator Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the LOL output goes to logic
1. The LOL pin will return back to logic 0 when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines Using LOL
As described, the LOL pin indicates when the PLL is
out-of-lock with the input reference. The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features). To ensure reliable
operation of LOL and guard against false out-of-lock
indications, the following conditions should be met:
The phase detector frequency should be no less than
5MHz, and preferably it should be 10MHz or greater.
Phase detector frequency is defined by Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
LOL phase detector. Refer to Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1040-11-155.5200.
The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL.
Reference Acknowledgement (REF_ACK) Output
The REF_ACK (reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic 1 indicates input pair 1
(nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0
(nDIF_REF0, DIF_REF0). The REF_ACK indicator is an
LVCMOS output.
M1040 Datasheet Rev 0.1
5 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400