PIN SYMBOL TYPE
O Receive Channel Clock. 192 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
O Receive Serial Data. Received NRZ serial data; updated on rising
edges of RCLK.
25 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR2.4=0) or multiframe
boundaries (RCR2.4=1). If set to output frame boundaries, then via
RCR2.5, RSYNC can also be set to output double-wide pulses on
signaling frames. If the elastic store is enabled via the CCR1.2, then
this pin can be enabled to be an input via RCR2.3 at which a frame
boundary pulse is applied. See Section 13 for timing details.
I Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.
Tie together to receive NRZ data and disable bipolar violation
I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when
the elastic store function is enabled via the CCR. Should be tied low
in applications that do not use the elastic store.
O Serial Port Data for the Line Interface. Connects directly to the
SDI input pin on the line interface.
O Serial Port Clock for the Line Interface. Connects directly to the
SCLK input pin on the line interface.
O Serial Port Chip Select for the Line Interface. Connects directly
to the CS input pin on the line interface.
O Receive/Transmit Channel Block. A user-programmable output
that can be forced high or low during any of the 24 T1 channels.
Useful for blocking clocks to a serial UART or LAPD controller in
application where not all T1 channels are used such as Fractional
T1, 384K bps service, 768K bps, or ISDN-PRI. Also useful for
locating individual channels in drop-and-insert applications. See
Section 13 for timing details.
34 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If CCR1.6=0, then this pin will toggle high when the
synchronizer is searching for the T1 frame and multiframe. If
CCR1.6=1, then this pin will toggle high when the TCLK pin has
not been toggled for 5 ms.
O Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
O Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain
O Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for
the TLINK input. See Section 13 for timing details.
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