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DS2154
Enhanced E1 Single Chip Transceiver
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long- and short-haul line interface for
clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Generates line build outs for both 120=and
75=lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1,
H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits aligned with
CRC multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single-
Chip Transceiver
5V supply; low power CMOS
100-pin 14mm2 body LQFP package
PACKAGE OUTLINE
1
ORDERING INFORMATION
DS2154L
(0°C to 70°C)
DS2154LN
(-40°C to +85°C)
DESCRIPTION
The DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to
over 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can access
to control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
G.704, G.706, G.823, G.932, and I.431 as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
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112099

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TABLE OF CONTENTS
DS2154
1.0 INTRODUCTION ............................................................................................................. 4
New Features................................................................................................................................... 4
Block Diagram ................................................................................................................................ 5
Pin List ............................................................................................................................................ 7
Pin Description.............................................................................................................................. 10
Register Map ................................................................................................................................. 15
2.0 PARALLEL PORT ........................................................................................................ 20
3.0 CONTROL, ID, AND TEST REGISTERS...................................................................... 20
SYNC/RESYNC Criteria.............................................................................................................. 22
Framers Loopback......................................................................................................................... 27
Automatic Alarm Generation........................................................................................................ 28
Power-up Sequence....................................................................................................................... 30
Remote Loopback ......................................................................................................................... 31
Local Loopback............................................................................................................................. 31
4.0 STATUS AND INFORMATION REGISTERS................................................................ 32
CRC 4 SYNC Counter .................................................................................................................. 35
Alarm Criteria ............................................................................................................................... 36
5.0 ERROR COUNT REGISTERS ...................................................................................... 40
BPV or Code Violation Counter ................................................................................................... 40
CRC4 Error Counter ..................................................................................................................... 41
E-bit Counter................................................................................................................................. 41
FAS Error Counter ........................................................................................................................ 42
6.0 DSO MONITORING FUNCTION ................................................................................... 43
7.0 SIGNALING OPERATION ............................................................................................ 46
Processor Based Signaling ............................................................................................................ 46
Hardware Based Signaling............................................................................................................ 49
8.0 PER-CHANNEL CODE GENERATION ........................................................................ 51
Transmit Side Code Generation.................................................................................................... 51
Receive Side Code Generation ..................................................................................................... 53
9.0 CLOCK BLOCKING REGISTERS ................................................................................ 54
10.0 ELASTIC STORES OPERATION ................................................................................. 56
11.0
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION .............................. 57
Hardware Scheme ......................................................................................................................... 57
Internal Register Scheme Based on Double-Frame ...................................................................... 57
Internal Register Scheme Based on CRC4 Multiframe ................................................................ 60
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12.0
DS2154
LINE INTERFACE FUNCTIONS ................................................................................... 62
Receive Clock and Data Recovery................................................................................................ 62
Transmit Waveshaping and Line Driving..................................................................................... 63
Jitter Attenuator............................................................................................................................. 64
13.0 TIMING DIAGRAMS...................................................................................................... 67
Synchronization Flowchart ........................................................................................................... 72
Transmit Data Flow Diagram ....................................................................................................... 73
14.0
CHARACTERISTICS .................................................................................................... 74
Absolute Maximum Rating........................................................................................................... 74
DC Parameters .............................................................................................................................. 74
AC Parameters .............................................................................................................................. 75
Timing........................................................................................................................................... 77
Package Description...................................................................................................................... 85
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DS2154
1.0 INTRODUCTION
The DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2153 have been retained and software created
for the original devices is transferable into the DS2154.
NEW FEATURES
Option for non-multiplexed bus operation
Crystal-less jitter attenuation
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
Interrupt generated on change of signaling data
Improved receive sensitivity: 0 dB to -43 dB
Per-channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192 MHz clock synthesizer
Per-channel loopback
Addition of hardware pins to indicate carrier loss and signaling freeze
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50 mA short circuit requirement
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
SECTION
1 and 2
12
7
12
8
11
4
1
8
1
1
1
6
1
1 and 3
12
3
3
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DS2154 ENHANCED E1 SINGLE-CHIP TRANSCEIVER Figure 1-1
DS2154
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