DS2180A.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 DS2180A 데이타시트 다운로드

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FEATURES
Single chip DS1 rate transceiver
Supports common framing standards
– 12 frames/superframe “193S”
– 24 frames/superframe “193E”
Three zero suppression modes
– B7 stuffing
– B8ZS
– Transparent
Simple serial interface used for config-
uration, control and status monitoring in
“processor” mode
=“Hardware” mode requires no host
processor; intended for stand-alone app-
lications
Selectable 0, 2, 4, 16 state robbed bit
signaling modes
Allows mix of “clear” and “non-clear” DS0
channels on same DS1 link
Alarm generation and detection
Receive error detection and counting for
transmission performance monitoring
5V supply, low-power CMOS technology
Surface-mount package available, designated
DS2180AQ
Industrial temperature range of -40°C to
+85°C available, designated DS2180AN or
DS2180AQN
Compatible to DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2175 T1/CEPT
Elastic Store, DS2290 T1 Isolation Stik, and
DS2291 T1 Long Loop Stik
DS2180A
T1 Transceiver
PIN ASSIGNMENT
TMSYNC
TFSYNC
TCLK
TCHCLK
TSER
TMO
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
INT
SDI
SDO
CS
SCLK
SPS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 RLOS
38 RFER
37 RBV
36 RCL
35 RNEG
34 RPOS
33 RST
32 TEST
31 RSIGSEL
30 RSIGFR
29 RABCD
28 RMSYNC
27 RFSYNC
26 RSER
25 RCHCLK
24 RCLK
23 RLCLK
22 RLINK
21 RYEL
40-Pin DIP (600-mil)
TSER
TMO
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
INT
SDI
7
8
9
10
11
12
13
14
15
16
17
39 RNEG
38 RPOS
37 RST
36 TEST
35 RSIGSEL
34 RSIGFR
33 RABCD
32 RMSYNC
31 RFSYNC
30 RSER
29 RCHCLK
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DS1386/DS1386P
DESCRIPTION
The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier
transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12
frames/superframe). The 193E framing mode supports the extended superframe format (24
frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression
and signaling modes.
Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate
framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides
output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and
multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and
transmission errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero
suppression, alarm and signaling formats. User access to the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port
which can be used for device configuration, control and status monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into “hard-
wired” select pins. Features such as selection “clear” DS0 channels, insertion of idle code and alteration
of sync algorithm are unavailable in the hardware mode.
DS2180A BLOCK DIAGRAM Figure 1
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DS2180A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN SYMBOL TYPE
DESCRIPTION
1 TMSYNC
I Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2 TFSYNC
I Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3 TCLK
I Transmit Clock. 1.544 MHz primary clock.
4 TCHCLK
O Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5 TSER
I Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6 TMO
O Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7 TSIGSEL
O Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8 TSIGFR
O Transmit Signaling Frame. High during signaling frames, low otherwise.
9 TABCD
I Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10 TLINK
I Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193S-
External S-Bit insertion).
11 TLCLK
O Transmit Link Clock. 4 kHz demand clock for TLINK input.
12 TPOS
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
13 TNEG
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN SYMBOL TYPE
DESCRIPTION
14 INT 1
O Receive Alarm Interrupt. Flags host controller during alarm conditions. Active
low, open drain output.
15 SDI1
16 SDO1
I Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
O Serial Data Out. Control and status information from onboard registers. Updated
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
17 CS 1
18 SCLK1
19 SPS
I Chip Select. Must be low to write or read the serial port registers.
I Serial Data Clock. Used to write or read the serial port registers.
I Serial Port Select. Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
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POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN SYMBOL TYPE
DESCRIPTION
20 VSS
32 TEST
40 VDD
- Signal Ground. 0.0 volts.
I Test Mode. Tie to VSS for normal operation.
- Positive Supply. 5.0 volts.
DS2180A
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN SYMBOL TYPE
DESCRIPTION
21 RYEL
0 Receive Yellow Alarm. Transitions high when yellow alarm detected, goes low
when alarm clears.
22 RLINK
0 Receive Link Data. Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
23 RLCLK
0 Receive Link Clock. 4 kHz demand clock for RLINK.
24 RCLK
I Receive Clock. 1.544 MHz primary clock.
25 RCHCLK
O Receive Channel Clock. 192 kHz clock identifies time slot (channel) boundaries.
26 RSER
O Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK.
27 RFSYNC
O Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
28 RMSYNC
O Receive Multiframe Sync. Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
29 RABCD
O Receive ABCD Signaling. Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
30 RSIGFR
O Receive Signaling Frame. High during signaling frames, low during resync and
non-signaling frames.
31 RSIGSEL
O Receive Signaling Select. In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
33 RST
I Reset. A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
34 RPOS
35 RNEG
I Receive Bipolar Data Inputs. Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
36 RCL
O Receive Carrier Loss. High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
37 RBV
O Receive Bipolar Violation. High during accused bit time at RSER if bipolar
violation detected, low otherwise.
38 RFER
O Receive Frame Error. High during F-Bit time when FT or FS errors occur (193S)
or when FPS or CRC errors occur (193E). Low during resync.
39 RLOS
O Receive Loss of Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
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DS2180A
REGISTER SUMMARY Table 5
REGISTER
RSR
RIMR
ADDRESS
0000
0001
T/R1
R2
R
DESCRIPTION/FUNCTION
Receive Status Register. Reports all receive alarm conditions.
Receive Interrupt Mask Register. Allows masking of individual alarm-
generated interrupts.
BVCR
0010
R Bipolar Violation Count Register. 8-bit presettable counter which records
individual bipolar violations.
ECR
CCR3
RCR3
TCR3
0011
0100
0101
0110
R Error Count Register. Two independent 4-bit counters which record OOF
occurrences and individual frame bit or CRC errors.
T/R Common Control Register. Selects device operating characteristics common
to receive and transmit sides.
R Receive Control Register. Programs device operating characteristics
unique to the receive side.
T Transmit Control Register. Selects additional transmit side modes.
TIR1
TIR2
0111
1000
T Transmit Idle Registers. Designate which outgoing channels are to be
T substituted with idle code.
TIR3
1001
T
TTR1
TTR2
1010
1011
T Transmit Transparent Registers. Designate which outgoing channels are to be
T treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
TTR3
1100
T
RMR1
RMR2
1101
1110
R Receive Mark Registers. Designate which incoming channels are to be replaced
R with idle or digital milliwatt codes (under control of RCR).
RMR3
1111
R
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.
Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held on the next falling edge.
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