REGISTER SUMMARY Table 5
Receive Status Register. Reports all receive alarm conditions.
Receive Interrupt Mask Register. Allows masking of individual alarm-
R Bipolar Violation Count Register. 8-bit presettable counter which records
individual bipolar violations.
R Error Count Register. Two independent 4-bit counters which record OOF
occurrences and individual frame bit or CRC errors.
T/R Common Control Register. Selects device operating characteristics common
to receive and transmit sides.
R Receive Control Register. Programs device operating characteristics
unique to the receive side.
T Transmit Control Register. Selects additional transmit side modes.
T Transmit Idle Registers. Designate which outgoing channels are to be
T substituted with idle code.
T Transmit Transparent Registers. Designate which outgoing channels are to be
T treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
R Receive Mark Registers. Designate which incoming channels are to be replaced
R with idle or digital milliwatt codes (under control of RCR).
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.
Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
Reading or writing the control, configuration or status registers requires writing one address command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held on the next falling edge.
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