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INTEGRATED CIRCUITS
74ALVT16600
2.5V/3.3V 18-bit universal bus
transceiver (3-State)
Product specification
Replaces data of 1997 May 12
IC23 Data Handbook
1998 Feb 13
Philips
Semiconductors

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Philips Semiconductors
2.5V/3.3V 18-bit universal bus transceiver (3-State)
Product specification
74ALVT16600
FEATURES
18-bit bidirectional bus interface
5V I/O Compatible
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Negative edge-triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16600 is a high-performance BiCMOS product
designed for VCC operation at 2.5V and 3.3V with I/O compatibility
up to 5V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The High clock can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Input capacitance DIR, OE
I/O pin capacitance
Total supply current
CONDITIONS
Tamb = 25°C
CL = 50pF
VI = 0V or VCC
Outputs disabled; VI/O = 0V or VCC
Outputs disabled
TYPICAL
2.5V
3.3V
1.9 1.6
2.5 1.9
44
88
40 70
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVT16600 DL
–40°C to +85°C
74ALVT16600 DGG
NORTH AMERICA
AV16600 DL
AV16600 DGG
DWG NUMBER
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
1, 27
29, 56
2, 28
55,30
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
OEAB/OEBA
CEBA/CEAB
LEAB/LEBA
CPAB/CPBA
A0-A17
B0-B17
GND
VCC
NAME AND FUNCTION
A-to-B Output enable input (active Low)
B-to-A / A-to-B clock enable (active Low)
A-to-B/B-to-A Latch enable input
A-to-B/B-to-A Clock input (active falling edge)
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Ground (0V)
Positive supply voltage
1998 Feb 13
2 853-1979 18958

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Philips Semiconductors
2.5V/3.3V 18-bit universal bus transceiver (3-State)
Product specification
74ALVT16600
FUNCTION TABLE
INPUTS
OUTPUT
CEAB
OEAB LEAB CPAB
A
B
X
H X XX
Z
X
L H XL
L
X
L H XH
H
H L L X X BO
L
L L L
L
L
L L H
H
L L L H X BO
L L L L X B
X =Don’t care
H =High voltage level
L = Low voltage level
=High-to-Low clock transition
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CPBA, and CEBA.
 Output level before the indicated steady-state input conditions
were established.
§ Output level before the indicated steady-state input conditions
were established, provided that CLKAB was Low before LEAB
went Low.
PIN CONFIGURATION
OEAB 1
LEAB 2
A0 3
GND 4
A1 5
A2 6
VCC
A3
7
8
A4 9
A5 10
GND 11
A6 12
A7 13
A8 14
A9 15
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
VCC 22
A15 23
A16 24
GND 25
A17 26
OEBA 27
LEBA 28
56 CEAB
55 CPAB
54 B0
53 GND
52 B1
51 B2
50 VCC
49 B3
48 B4
47 B5
46 GND
45 B6
44 B7
43 B8
42 B9
41 B10
40 B11
39 GND
38 B12
37 B13
36 B14
35 VCC
34 B15
33 B16
32 GND
31 B17
30 CPBA
29 CEBA
SW00191
1998 Feb 13
3

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Philips Semiconductors
2.5V/3.3V 18-bit universal bus transceiver (3-State)
Product specification
74ALVT16600
LOGIC DIAGRAM (Positive Logic)
1
OEAB
CEAB 56
CPAB 55
LEAB 2
LEBA 28
CPBA 30
CEBA 29
OEBA 27
A0 3
CE
ID
C1
CLK
CE
ID
C1
CLK
54 B0
To 17 other channels
SW00190
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
VCC
IIK
VI
IOK
VOUT
IOUT
DC supply voltage
DC input diode current
DC input voltage3
DC output diode current
DC output voltage3
DC output current
VI < 0
VO < 0
Output in Off or High state
Output in Low state
Output in High state
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
–64
V
mA
V
mA
V
mA
Tstg Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
1998 Feb 13
4

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Philips Semiconductors
2.5V/3.3V 18-bit universal bus transceiver (3-State)
Product specification
74ALVT16600
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VIH
VIL
IOH
IOL
t/v
Tamb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle 50%; f 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
2.5V RANGE LIMITS
MIN MAX
2.3 2.7
0 5.5
1.7
0.7
–8
8
24
10
–40 +85
3.3V RANGE LIMITS
MIN MAX
3.0 3.6
0 5.5
2.0
0.8
–32
32
64
10
–40 +85
UNIT
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C UNIT
MIN TYP1 MAX
VIK
VOH
VOL
VRST
II
IOFF
IHOLD
IEX
IPU/PD
Input clamp voltage
High-level output voltage
Low–level output voltage
Power-up output low voltage6
Input leakage current
Off current
Bus Hold current
Data inputs7
Current into an output in the
High state when VO > VCC
Power up/down 3-State output
current3
VCC = 3.0V; IIK = –18mA
VCC = 3.0 to 3.6V; IOH = –100µA
VCC = 3.0V; IOH = –32mA
VCC = 3.0V; IOL = 100µA
VCC = 3.0V; IOL = 16mA
VCC = 3.0V; IOL = 32mA
VCC = 3.0V; IOL = 64mA
VCC = 3.6V; IO = 1mA; VI = VCC or GND
VCC = 3.6V; VI = VCC or GND
VCC = 0 or 3.6V; VI = 5.5V
VCC = 3.6V; VI = 5.5V
VCC = 3.6V; VI = VCC
VCC = 3.6V; VI = 0V
VCC = 0V; VI or VO = 0 to 4.5V
VCC = 3V; VI = 0.8V
VCC = 3V; VI = 2.0V
VCC = 0V to 3.6V; VCC = 3.6V
Control pins
Data pins4
VO = 5.5V; VCC = 3.0V
VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC
OE = Don’t care
VCC–0.2
2.0
–0.85
VCC
2.3
0.07
0.25
0.3
0.4
75
–75
±500
0.1
0.1
0.1
0.5
0.1
0.1
130
–140
10
1.0
–1.2
0.2
0.4
0.5
0.55
0.55
±1
10
20
10
-5
±100
125
±100
V
V
V
V
µA
µA
µA
µA
µA
ICCH
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.06 0.1
ICCL Quiescent supply current
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
4.0 5 mA
ICCZ
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05
0.06 0.1
ICC
Additional supply current per
input pin2
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04 0.4 mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 13
5