FQA70N10.pdf 데이터시트 (총 8 페이지) - 파일 다운로드 FQA70N10 데이타시트 다운로드

No Preview Available !

FQA70N10
100V N-Channel MOSFET
August 2000
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
Features
• 70A, 100V, RDS(on) = 0.023@VGS = 10 V
• Low gate charge ( typical 85 nC)
• Low Crss ( typical 150 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
G DS
TO-3P
FQA Series
D
!
"
!"
G!
"
"
!
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
FQA70N10
100
70
49.5
280
± 25
1300
70
21.4
6.0
214
1.43
-55 to +175
300
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
Typ
--
0.24
--
Max
0.7
--
40
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
©2000 Fairchild Semiconductor International
Rev. B, August 2000

No Preview Available !

Electrical Characteristics
Symbol
Parameter
TC = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
/ TJ
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
IDSS
Zero Gate Voltage Drain Current
IGSSF
IGSSR
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25°C
VDS = 100 V, VGS = 0 V
VDS = 80 V, TC = 150°C
VGS = 25 V, VDS = 0 V
VGS = -25 V, VDS = 0 V
100
--
--
--
--
--
--
0.1
--
--
--
--
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
VGS(th)
RDS(on)
Gate Threshold Voltage
Static Drain-Source
On-Resistance
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 35 A
VDS = 40 V, ID = 35 A
(Note 4)
2.0 --
4.0
-- 0.019 0.023
-- 48
--
V
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 2500 3300
-- 720 940
-- 150 200
pF
pF
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = 50 V, ID = 70 A,
RG = 25
-- 30
70
-- 470 950
-- 130 270
(Note 4, 5)
--
160
330
VDS = 80 V, ID = 70 A,
-- 85 110
VGS = 10 V
-- 16
--
(Note 4, 5) --
42
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
-- -- 70
ISM Maximum Pulsed Drain-Source Diode Forward Current
-- -- 280
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 70 A
-- -- 1.5
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 70 A,
dIF / dt = 100 A/µs
-- 110
(Note 4) -- 430
--
--
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.4mH, IAS = 70A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 70A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
A
A
V
ns
nC
©2000 Fairchild Semiconductor International
Rev. B, August 2000

No Preview Available !

Typical Characteristics
V
GS
Top : 15.0 V
10.0 V
102 8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
101
100
10-1
Notes :
1. 250μs Pulse Test
2. TC = 25
100 101
V , Drain-Source Voltage [V]
DS
Figure 1. On-Region Characteristics
80
64
V = 10V
GS
48
V = 20V
GS
32
16
Note : TJ = 25
0
0 60 120 180 240 300
I , Drain Current [A]
D
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
7000
6000
5000
4000
3000
2000
1000
0
10-1
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
C
iss
Coss
Crss
Notes :
1. VGS = 0 V
2. f = 1 MHz
100 101
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
102
101 175
25
100
10-1
2
-55
Notes :
1. VDS = 40V
2. 250μs Pulse Test
468
VGS , Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
102
101
100
175
10-1
0.2
0.4
25
Notes :
1. VGS = 0V
2. 250μs Pulse Test
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V , Source-Drain Voltage [V]
SD
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10 V = 50V
DS
V = 80V
DS
8
6
4
2
Note : ID = 70A
0
0 10 20 30 40 50 60 70 80 90 100
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. B, August 2000

No Preview Available !

Typical Characteristics (Continued)
1.2
1.1
1.0
0.9
0.8
-100
Notes :
1. VGS = 0 V
2. ID = 250 μA
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
103 Operation in This Area
is Limited by R DS(on)
102 100 µs 10 µs
1 ms
10 ms
DC
101
100
10-1
100
Notes :
1. TC = 25 oC
2. TJ = 175 oC
3. Single Pulse
101
V , Drain-Source Voltage [V]
DS
102
Figure 9. Maximum Safe Operating Area
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. VGS = 10 V
2. ID = 35 A
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 8. On-Resistance Variation
vs. Temperature
70
60
50
40
30
20
10
0
25 50 75 100 125 150 175
TC, Case Temperature []
Figure 10. Maximum Drain Current
vs. Case Temperature
100
D = 0.5
1 0 -1
1 0 -2
0 .2
0 .1
0 .05
0 .02
0 .01
sin g le p u lse
N otes :
1.
Z
θ
(t)
JC
=
0 .7
/W
M ax.
2. D uty F a ctor, D =t /t
12
3.
T
JM
-
T
C
=
P
DM
*
Z
θ
(t)
JC
PDM
t1
t2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
t1, S q u a re W a ve P u lse D u ra tio n [se c]
101
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. B, August 2000

No Preview Available !

Gate Charge Test Circuit & Waveform
50KΩ
Same Type
as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
10V
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
10V
tp
Unclamped Inductive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS
=
--1--
2
L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
©2000 Fairchild Semiconductor International
Rev. B, August 2000