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FQB33N10L / FQI33N10L
100V LOGIC N-Channel MOSFET
September 2000
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as high efficiency
switching DC/DC converters, and DC motor control.
Features
• 33A, 100V, RDS(on) = 0.052@VGS = 10 V
• Low gate charge ( typical 30 nC)
• Low Crss ( typical 70 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
DD
!
GS
D2-PAK
FQB Series
GDS
I2-PAK
FQI Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TA = 25°C) *
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
"
!"
G!
"
"
!
S
FQB33N10L / FQI33N10L
100
33
23
132
± 20
430
33
12.7
6.0
3.75
127
0.85
-55 to +175
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
Parameter
RθJC
Thermal Resistance, Junction-to-Case
RθJA
Thermal Resistance, Junction-to-Ambient *
RθJA
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
Typ Max Units
-- 1.18 °C/W
-- 40 °C/W
-- 62.5 °C/W
©2000 Fairchild Semiconductor International
Rev. A, September 2000

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Electrical Characteristics
Symbol
Parameter
TC = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
/ TJ
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
VGS = 0 V, ID = 250 µA
100 --
ID = 250 µA, Referenced to 25°C -- 0.09
IDSS
Zero Gate Voltage Drain Current
VDS = 100 V, VGS = 0 V
VDS = 80 V, TC = 150°C
-- --
-- --
IGSSF
IGSSR
Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V
Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V
-- --
-- --
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
VGS(th) Gate Threshold Voltage
RDS(on) Static Drain-Source
On-Resistance
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 16.5 A
VGS = 5 V, ID = 16.5 A
VDS = 30 V, ID = 16.5 A
(Note 4)
1.0 --
2.0
--
0.039 0.052
0.043 0.055
-- 27
--
V
S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 1250 1630
-- 305 400
-- 70
90
pF
pF
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = 50 V, ID = 33 A,
RG = 25
-- 17
45
-- 470 950
-- 70 150
(Note 4, 5)
-- 120 250
VDS = 80 V, ID = 33 A,
VGS = 5 V
(Note 4, 5)
--
--
--
30
4.7
16
40
--
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
(Note 6)
--
--
33
ISM Maximum Pulsed Drain-Source Diode Forward Current
-- -- 132
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 33 A
-- -- 1.5
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 33 A,
dIF / dt = 100 A/µs
-- 90
(Note 4) -- 0.26
--
--
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.59mH, IAS = 33A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 33A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
A
A
V
ns
µC
©2000 Fairchild Semiconductor International
Rev. A, September 2000

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Typical Characteristics
102 Top :
V
GS
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
101
100
10-1
Notes :
1. 250μs Pulse Test
2. TC = 25
100
V , Drain-Source Voltage [V]
DS
101
Figure 1. On-Region Characteristics
0.20
0.16
V = 5V
GS
0.12
V = 10V
GS
0.08
0.04
0.00
0
Note : T = 25
J
30 60 90
ID, Drain Current [A]
120
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
3600
3000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2400
1800
1200
600
C
iss
C
oss
Crss
Notes :
1. VGS = 0 V
2. f = 1 MHz
0
10-1 100 101
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
102
101 175
25
100
10-1
0
-55
Notes :
1. VDS = 30V
2. 250μs Pulse Test
2468
VGS, Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
102
101
100
10-1
0.2
175
25
Notes :
1. V = 0V
GS
2. 250μs Pulse Test
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD, Source-Drain voltage [V]
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
V = 50V
DS
8
V = 80V
DS
6
4
2
Note : ID = 33A
0
0 10 20 30 40 50
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, September 2000

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Typical Characteristics (Continued)
1.2
1.1
1.0
0.9 Notes :
1. VGS = 0 V
2. ID = 250 μA
0.8
-100
-50 0
50 100 150
TJ, Junction Temperature [oC]
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area
is Limited by R DS(on)
102
100 µs
1 ms
10 ms
101 DC
100
100
Notes :
1. TC = 25 oC
2. TJ = 175 oC
3. Single Pulse
101
VDS, Drain-Source Voltage [V]
102
Figure 9. Maximum Safe Operating Area
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. VGS = 10 V
2. ID = 16.5 A
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 8. On-Resistance Variation
vs. Temperature
35
30
25
20
15
10
5
0
25 50 75 100 125 150 175
T , Case Temperature []
C
Figure 10. Maximum Drain Current
vs. Case Temperature
100
D =0 .5
0 .2
1 0 -1
0 .1
0 .0 5
0 .0 2
0 .0 1
s in g le p u ls e
N otes :
1.
Zθ
(t)
JC
=
1.1 8
/W
M ax.
2 . D u t y F a c t o r , D = t /t
12
3.
T
JM
-
T
C
=
P
DM
*
Zθ
(t)
JC
PDM
t1
t2
1 0 -2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]
101
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, September 2000

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Gate Charge Test Circuit & Waveform
50KΩ
Same Type
as DUT
12V 200nF
300nF
VGS
5V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
VGS
RG
RL
VDD
VDS
90%
5V
DUT
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
10V
tp
Unclamped Inductive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS
=
--1--
2
L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
©2000 Fairchild Semiconductor International
Rev. A, September 2000