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February 2001
FQD12N20L / FQU12N20L
200V LOGIC N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply, motor control.
Features
• 9.0A, 200V, RDS(on) = 0.28@VGS = 10 V
• Low gate charge ( typical 16 nC)
• Low Crss ( typical 17 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• Low level gate drive requirement allowing direct
opration from logic drivers
D
D!
GS
D-PAK
FQD Series
GDS
I-PAK
FQU Series
"
!"
G!
"
"
!
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TA = 25°C) *
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
FQD12N20L / FQU12N20L
200
9.0
5.7
36
± 20
210
9.0
5.5
5.5
2.5
55
0.44
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
RθJC
RθJA
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Typ Max Units
-- 2.27 °C/W
-- 50 °C/W
-- 110 °C/W
Rev. A1, February 2001

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Electrical Characteristics
Symbol
Parameter
TC = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
/ TJ
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
VGS = 0 V, ID = 250 µA
200 --
ID = 250 µA, Referenced to 25°C -- 0.14
IDSS
Zero Gate Voltage Drain Current
VDS = 200 V, VGS = 0 V
VDS = 160 V, TC = 125°C
-- --
-- --
IGSSF
IGSSR
Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V
Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V
-- --
-- --
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
VGS(th) Gate Threshold Voltage
RDS(on) Static Drain-Source
On-Resistance
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
1.0 --
2.0
VGS = 10 V, ID = 4.5 A
VGS = 5 V, ID = 4.5 A
--
0.22 0.28
0.25 0.32
VDS = 30 V, ID = 4.5 A (Note 4) -- 11.6
--
V
S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 830 1080 pF
-- 120 155
pF
-- 17 22 pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = 100 V, ID = 11.6 A,
RG = 25
-- 15
40
-- 190 390
-- 60 130
(Note 4, 5)
-- 120 250
VDS = 160 V, ID = 11.6 A,
VGS = 5 V
(Note 4, 5)
--
--
--
16
2.8
7.6
21
--
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
-- -- 9.0
ISM Maximum Pulsed Drain-Source Diode Forward Current
-- -- 36
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 9.0 A
-- -- 1.5
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 11.6 A,
-- 128
dIF / dt = 100 A/µs
(Note 4) -- 0.56
--
--
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 3.9mH, IAS = 9.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 11.6A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
A
A
V
ns
µC
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001

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Typical Characteristics
Top :
V
GS
10 V
8.0 V
101
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
100
10-1
10-1
Notes :
1. 250μs Pulse Test
2. T = 25
C
100 101
V , Drain-Source Voltage [V]
DS
Figure 1. On-Region Characteristics
1.5
1.2
VGS = 5 V
0.9
V = 10V
GS
0.6
0.3
0.0
0
6 12 18 24 30 36
ID , Drain Current [A]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
1800
1500
1200
900
600
300
0
10-1
C = C + C (C = shorted)
iss gs gd ds
C =C +C
oss ds gd
C =C
rss gd
C
iss
C
oss
C
rss
Notes :
1. V = 0 V
GS
2. f = 1 MHz
100 101
V , Drain-Source Voltage [V]
DS
Figure 5. Capacitance Characteristics
©2001 Fairchild Semiconductor Corporation
101
150
100 25
10-1
0
-55
Notes :
1. VDS = 30V
2. 250μs Pulse Test
2468
VGS, Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
101
100
10-1
0.2
15025
Notes :
1. V = 0V
GS
2. 250μs Pulse Test
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V , Source-Drain voltage [V]
SD
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
V = 40V
DS
V = 100V
DS
8
V = 160V
DS
6
4
2
Note : ID = 11.6 A
0
0 5 10 15 20 25 30
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A1, February 2001

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Typical Characteristics (Continued)
1.2
1.1
1.0
0.9
0.8
-100
Notes :
1. VGS = 0 V
2. ID = 250 μA
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
102 Operation in This Area
is Limited by R DS(on)
100 µs 10 µs
101 1 ms
10 ms
DC
100
10-1
100
Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
101 102
V , Drain-Source Voltage [V]
DS
Figure 9. Maximum Safe Operating Area
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. V = 10 V
GS
2. I = 5.8 A
D
-50 0
50 100 150
T , Junction Temperature [oC]
J
200
Figure 8. On-Resistance Variation
vs. Temperature
9.0
7.5
6.0
4.5
3.0
1.5
0.0
25 50 75 100 125 150
TC, Case Temperature []
Figure 10. Maximum Drain Current
vs. Case Temperature
100 D =0.5
1 0 -1
0 .2
0 .1
0 .05
0 .02
0 .01
s in g le p u ls e
N ote s :
1.
Z
θ
(t)
JC
=
2.27
/W
M ax.
2. D u ty F actor, D =t /t
12
3.
T
JM
-
T
C
=
P
DM
*
Z
θ
(t)
JC
PDM
t1
t2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
101
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001

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Gate Charge Test Circuit & Waveform
50KΩ
Same Type
as DUT
12V 200nF
300nF
VGS
5V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
VGS
RG
RL
VDD
VDS
90%
5V
DUT
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
10V
tp
Unclamped Inductive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS
=
--1--
2
L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001