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FQD17N08 / FQU17N08
80V N-Channel MOSFET
January 2001
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for low voltage applications such as automotive,
high efficiency switching for DC/DC converters, and DC
motor control.
Features
• 12.9A, 80V, RDS(on) = 0.115@VGS = 10 V
• Low gate charge ( typical 12 nC)
• Low Crss ( typical 28 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
D
D!
GS
D-PAK
FQD Series
GDS
I-PAK
FQU Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TA = 25°C) *
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
"
!"
G!
"
"
!
S
FQD17N08 / FQU17N08
80
12.9
8.2
51.6
± 25
100
12.9
4.0
6.5
2.5
40
0.32
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
RθJC
RθJA
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Typ Max Units
-- 3.13 °C/W
-- 50 °C/W
-- 110 °C/W
Rev. A1, January 2001

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Electrical Characteristics
Symbol
Parameter
TC = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
/ TJ
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
VGS = 0 V, ID = 250 µA
80 -- -- V
ID = 250 µA, Referenced to 25°C -- 0.08 -- V/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 80 V, VGS = 0 V
VDS = 64 V, TC = 125°C
-- -- 1 µA
-- -- 10 µA
IGSSF
IGSSR
Gate-Body Leakage Current, Forward VGS = 25 V, VDS = 0 V
Gate-Body Leakage Current, Reverse VGS = -25 V, VDS = 0 V
-- -- 100 nA
-- -- -100 nA
On Characteristics
VGS(th)
RDS(on)
Gate Threshold Voltage
Static Drain-Source
On-Resistance
gFS Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 6.45 A
VDS = 30 V, ID = 6.45 A (Note 4)
2.0 --
4.0
-- 0.088 0.115
-- 5.17 --
V
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 350 450
-- 120 155
-- 28
35
pF
pF
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = 40 V, ID = 16.5 A,
RG = 25
(Note 4, 5)
VDS = 64 V, ID = 16.5 A,
VGS = 10 V
(Note 4, 5)
--
--
--
--
--
--
--
4.8 20
60 130
15 40
25 60
12 15
2.7 --
5.4 --
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
ISM Maximum Pulsed Drain-Source Diode Forward Current
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 12.9 A
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
VGS = 0 V, IS = 16.5 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.83mH, IAS = 12.9A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 16.5A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
--
--
--
--
--
-- 12.9
-- 51.6
-- 1.5
55 --
92 --
A
A
V
ns
nC
©2000 Fairchild Semiconductor International
Rev. A1, January 2001

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Typical Characteristics
V
GS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
101
5.5 V
5.0 V
Bottom : 4.5 V
100
10-1
Note :
1. 250μs Pulse Test
2. TC = 25
100
V , Drain-Source Voltage [V]
DS
101
Figure 1. On-Region Characteristics
0.4
0.3
V = 10V
GS
V = 20V
GS
0.2
0.1
Note : T = 25
J
0.0
0
10 20 30 40 50
ID, Drain Current [A]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
900
750
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
600
C Notes :
450
iss 1. VGS = 0 V
C 2. f = 1 MHz
oss
300
Crss
150
0
10-1 100 101
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
101
150
100 25
10-1
2
-55
Notes :
1. VDS = 30V
2. 250μs Pulse Test
468
V , Gate-Source Voltage [V]
GS
10
Figure 2. Transfer Characteristics
101
100
10-1
0.2
150
25
Note :
1. VGS = 0V
2. 250μs Pulse Test
0.4 0.6 0.8 1.0 1.2
V , Source-Drain Voltage [V]
SD
1.4
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
V = 40V
DS
VDS = 64V
8
6
4
2
Note : ID = 16.5A
0
0 2 4 6 8 10 12
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A1, January 2001

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Typical Characteristics (Continued)
1.2
1.1
1.0
0.9
0.8
-100
Notes :
1. VGS = 0 V
2. ID = 250 μA
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area
102 is Limited by R DS(on)
100 µs
1 ms
101
10 ms
DC
100
10-1
100
Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
101
V , Drain-Source Voltage [V]
DS
102
Figure 9. Maximum Safe Operating Area
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. VGS = 10 V
2. ID = 6.45 A
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 8. On-Resistance Variation
vs. Temperature
15
12
9
6
3
0
25 50 75 100 125 150
TC, Case Temperature []
Figure 10. Maximum Drain Current
vs. Case Temperature
D =0.5
100
0 .2
0 .1
0 .05
1 0 -1
0 .02
0 .01
s in g le p u ls e
N ote s :
1.
Z
θ
(t)
JC
=
3.13
/W
M ax.
2. D u ty F actor, D =t /t
12
3.
T
JM
-
T
C
=
P
DM
*
Z
θ
(t)
JC
PDM
t1
t2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
101
©2000 Fairchild Semiconductor International
Rev. A1, January 2001

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Gate Charge Test Circuit & Waveform
50KΩ
Same Type
as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
10V
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
10V
tp
Unclamped Inductive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS
=
--1--
2
L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
©2000 Fairchild Semiconductor International
Rev. A1, January 2001