AY0438.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 AY0438 데이타시트 다운로드

No Preview Available !

AY0438
32-Segment CMOS LCD Driver
FEATURES
• Drives up to 32 LCD segments of arbitrary config-
uration
• CMOS process for: wide supply voltage range,
low- power operation, high-noise immunity, wide
temperature range
• CMOS and TTL-compatible inputs
• Electrostatic discharge protection on all pins
• Cascadable
• On-chip oscillator
• Requires only three control lines
APPLICATIONS
• Industrial displays
• Consumer product displays
• Telecom product displays
• Automotive dashboard displays
DESCRIPTION
The AY0438 is a CMOS integrated device that drives a
liquid crystal display, usually under microprocessor
control. The part acts as a smart peripheral that drives
up to 32 LCD segments. It needs only three control
lines due to its serial input construction. It latches the
data to be displayed and relieves the microprocessor
from the task of generating the required waveforms.
The AY0438 can drive any standard or custom parallel
drive LCD display, whether it be field effect or dynamic
scattering; 7-, 9-, 14- or 16-segment characters; deci-
mals; leading + or -; or special symbols. Several
AY0438 devices can be cascaded. The AC frequency
of the LCD waveforms can either be supplied by the
user or generated by attaching a capacitor to the LCD
input, which controls the frequency of an internal oscil-
lator.
The AY0438 is available in 40-lead dual in-line plastic
and 44-lead PLCC packages. Unpackaged dice are
also available.
PIN CONFIGURATION
40-Lead Dual In-line
VDD
LOAD
SEG 32
SEG 31
SEG 30
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
SEG 20
SEG 19
SEG 18
SEG 17
SEG 16
SEG 15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CLOCK
SEG 1
SEG 2
SEG 3
VSS
DATA OUT
DATA IN
SEG 4
SEG 5
LCDΦ
BP
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
44 PLCC
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
SEG 20
SEG 19
7 39
8 38
9 37
10 36
11 35
12
13
AY0438
34
33
14 32
15 31
16 30
17 29
NC
DATA OUT
DATA IN
SEG 4
SEG 5
LCDΦ
BP
SEG 6
SEG 7
SEG 8
NC
© 1995 Microchip Technology Inc.
DS70010I-page 1

No Preview Available !

AY0438
FIGURE 1: PIN DESCRIPTIONS
Pin # (PDIP Only)
1
2
3-29, 32, 33, 37-39
30
31
34
35
36
40
Name
VDD
Load
Seg 1-32
BP
LCDΦ
Data In
Data Out
VSS
Clock
Direction
-
Input
Output
Output
Input
Input
Output
Ground
Input
Description
Supply voltage
Latch data from registers
Direct drive outputs
Backplane drive output
Backplane drive input
Data input to shift register
Data output from shift register
Ground
System clock input
FIGURE 2: BLOCK DIAGRAM
Data in
Clock
32-bit Static Shift Register
Load
32 Latches
Data out
FIGURE 3: BACKPLANE AND SEGMENT
OUTPUT
SEG On
32 Segment Drivers
LCDΦ
LCD AC
Generator
32 Outputs
Backplane
output
Backplane
SEG Off
FIGURE 4: TIMING DIAGRAM
CLOCK
Data in
Data out
Load
START
1
SEG 32
1/f
31
SEG 2
32
SEG 1
tDS tDH
tPD
tPW
1.0 OPERATION:
1.1 Data In and Clock
The shift register shifts and outputs on the falling edge
of the clock. Every clock falling edge does a logical left
shift. As an example, if 32 clock pulses are supplied as
in Figure 4, then the data input at the first clock will out-
put at SEG 32, and the last data input (# 32) will output
at SEG 1 when a LOAD signal is enabled (Figure 2). It
is recommended that a complete 32 bit transfer be
done every time the outputs are updated. A logic 1 at
the Data In causes the corresponding segment to be
DS70010I-page 2
enabled or visible, i.e. the output at Segment Output is
180° out-of-phase with the Backplane output
(Figure 3).
1.2 Load
A logic 1 at the Load input (Figure 2) causes the paral-
lel load of the data in the shift register into the latches
that control the segment drivers. If the Load signal is
tied high, then the latches become transparent and the
segment drivers are always connected to the shift reg-
isters.
© 1995 Microchip Technology Inc.

No Preview Available !

AY0438
1.3 LCDφ
LCDφ can be driven by an external signal or by con-
necting a capacitor between LCDφ and ground (GND),
which will enable the on-chip oscillator required to gen-
erate the backplane output voltage. Figure 5 shows the
relationship between capacitance value and output fre-
quency. Leaving the LCDφ input unconnected is not
recommended. When driven by an external clock, the
backplane output is in phase with the input clock. When
cascading two AY0438 devices (Figure 6 and
Figure 7), the backplane output can be generated
using a capacitor to GND on the first AY0438. This
backplane output can then be connected to the LCDφ
input of the second AY0438. The backplane output of
the second device is then used to drive the backplane
of the LCD module.
FIGURE 6: CASCADING TWO AY0438 DEVICES
FIGURE 5: OSCILLATOR FREQUENCY
GRAPH (TYPICAL @ 25°C)
140
120
100
80
60
40
0
20 40 60 80 100 120
CL (pF)
Data
in
Clock
Load
Clock
Load
Data
32-bit Static Shift Register out
32 Latches
Data
in Clock
Load
32-bit Static Shift Register
32 Latches
Data
out
LCDΦ
32 Segment Drivers
LCD AC
Generator
Backplane
output
1 to 32
Outputs
LCDΦ
32 Segment Drivers
LCD AC
Generator
Backplane
output
33 to 64
Outputs
FIGURE 7: CASCADE TIMING DIAGRAM
CLOCK
Data in
Data out
Load
START
1
SEG 64
1/f
63
SEG 2
64
SEG 1
tDS tDH
tPD
tPW
© 1995 Microchip Technology Inc.
DS70010I-page 3

No Preview Available !

AY0438
1.4 General
In order to avoid any race conditions, the Data In and
Load signals should not be changed during a falling
edge of the Clock. Figure 4 and Figure 7 show a typical
timing diagram for a 32 segment and 64 segment LCD
module.
1.5 Interfacing to a LCD Module and
PIC16CXX Device
Figure 8 shows a typical layout of an AY0438 con-
nected to a LCD module and interfaced to a PIC16CXX
family device. Example 1 lists code used to program
the PIC16CXX device. This code was complied using
MPASM.
FIGURE 8: INTERFACING TO A LCD MODULE AND PIC16CXX DEVICE
PIC16CXX
RB0
RB1
RB2
RB7
AY0438 SEG1
SEG7
SEG6
SEG5
Clock
SEG4
SEG3
SEG2
Data In
SEG9-15
Load
SEG19-23
SEG25-31
Backplane
LCDΦ
SEG A
SEG F
SEG G
SEG E
SEG D
SEG C
SEG B
A
FGB
EC
D
7
7
7
LCD
Backplane
EXAMPLE 1: EXAMPLE CODE
;*************************************************************************
;This program shows an interface between a PIC16CXX device
;and the AY0438 LCD controller to control a 7 Segment
;4 digit LCD module.
;The PIC16CXX interface to the AY0438 Hardware:
;
; PORTB bit 0 --> CLK
; PORTB bit 1 --> DATA IN
; PORTB bit 2 --> LOAD
;
;The LCD module is connected to the AY0438 as follows:
; Most Significant digit --> seg1 to seg7
; 3rd Significant digit --> seg9 to seg15
; 2nd Significant digit --> seg17 to seg 23
; Least Significant digit --> seg25 to seg 31
;
DS70010I-page 4
© 1995 Microchip Technology Inc.

No Preview Available !

AY0438
;The DP are not connected, but can be connected to seg8, 16, 24 & 32.
;For each digit, the segments are connected as:
; Seg A --> seg(8*n + 1)
; Seg B --> seg(8*n + 2)
; Seg C --> seg(8*n + 3)
; Seg D --> seg(8*n + 4)
; Seg E --> seg(8*n + 5)
; Seg F --> seg(8*n + 6)
; Seg G --> seg(8*n + 7)
;where n = 0, 1, 2 and 3 for MSD, 3rdSD, 2ndSD and LSD respectively.
;The firmware uses the values in registers:
; MSD, THRDSD, SCNDSD and LSD to determine the values to be
;pulsed to the AY0438.
;In this example, a pushbutton connected to PORTB bit 7
;is checked periodically to see if it has been pressed. If so,
;the LCD values in locations MSD to LSD are updated.
;*************************************************************************
list p=16c71,f=inhx8m
;
;
MSD equ 0x20
THRDSD equ
0x21
SCNDSD equ
0x22
LSD equ 0x23
count equ
0x24
temp equ
0x25
PORTB equ
0x06
#define CLK
PORTB,0
#define DATAIN PORTB,1
#define LOAD PORTB,2
#define UPDATELCD PORTB,7
w equ 0
STATUS equ
0x03
C equ 0
RP0 equ 5
OPTION equ
0x81
RBPU equ
7
PCL equ 0x02
PCLATH equ
0x0A
;
;
org 0
goto start
org 0x10
;
;This DecodeValue table must reside in page 0 for this program to work
;
DecodeValue
addwf PCL
retlw B'00111111'
;decode for 0
retlw B'00000110'
;decode for 1
retlw B'01011011'
;decode for 2
retlw B'01001111'
;decode for 3
retlw B'01100110'
;decode for 4
retlw B'01101101'
;decode for 5
© 1995 Microchip Technology Inc.
DS70010I-page 5