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July 1998
54ABT16374
16-Bit D Flip-Flop with TRI-STATE® Outputs
General Description
The ABT16374 contains sixteen non-inverting D flip-flops
with TRI-STATE outputs and is intended for bus oriented ap-
plications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
Features
n Separate control logic for each byte
n 16-bit version of the ABT374
n Edge-triggered D-type inputs
n Buffered Positive edge-triggered clock
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Guaranteed latch-up protection
n Standard Microcircuit Drawing (SMD) 5962-9320101
Ordering Code:
Commercial
54ABT16374W-QML
Package
Number
WA48A
48-Lead Cerpack
Package Description
Connection Diagram
Logic Symbol
Pin Assignment for Cerpack
Pin Description
DS100224-1
Pin
Names
OEn
CPn
D0– D15
O0– O15
Description
TRI-STATE Output Enable Input (Active Low)
Clock Pulse Input (Active Rising Edge)
Data Inputs
TRI-STATE Outputs
DS100224-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100224
PrintDate=1998/07/14 PrintTime=11:05:34 43604 ds100224 Rev. No. 1 cmserv Proof
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Functional Description
The ABT16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The device is byte controlled with each byte functioning iden-
tically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. Each byte
has a buffered clock and buffered Output Enable common to
all flip-flops within that byte. The description which follows
applies to each byte. Each flip-flop will store the state of their
individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CPn) transition. With the
Output Enable (OEn) LOW, the contents of the flip-flops are
available at the outputs. When OEn is HIGH, the outputs go
to the high impedance state. Operation of the OEn input
does not affect the state of the flip-flops.
Logic Diagrams
Truth Tables
Inputs
CP1
N
OE1
L
NL
LL
XH
Inputs
CP2
N
OE2
L
NL
LL
XH
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Byte 1 (0:7)
D0– D7
H
L
X
X
D8– D15
H
L
X
X
Outputs
O0– O7
H
L
(Previous)
Z
Outputs
O8– O15
H
L
(Previous)
Z
Byte 2 (8:15)
DS100224-3
DS100224-4
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Absolute Maximum Ratings (Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
−65˚C to +150˚C
−55˚C to +125˚C
−55˚C to +175˚C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to 5.5V
−0.5V to VCC
twice the rated IOL (mA)
DC Electrical Characteristics
DC Latchup Source Current:
OE Pin
(Across Comm Operating Range)
Other Pins
Over Voltage Latchup (I/O)
−350 mA
−500 mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
−55˚C to +125˚C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(V/t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
IIL
VID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
54ABT
54ABT
54ABT
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
ABT16374
Min Typ Max
2.0
0.8
−1.2
2.5
2.0
0.55
5
5
7
−5
−5
4.75
Units
V
V
V
V
V
V
µA
µA
µA
V
IOZH
IOZL
IOS
ICEX
IZZ
ICCH
ICCL
ICCZ
ICCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
−100
Output High Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional ICC/Input Outputs Enabled
Outputs TRI-STATE
Outputs TRI-STATE
50
−50
−275
50
100
2.0
62
2.0
2.5
2.5
2.5
µA
µA
mA
µA
µA
mA
mA
mA
mA
mA
mA
ICCD
Dynamic ICC
(Note 4)
No Load
mA/
0.30 MHz
Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
VCC
Min
Min
Min
Min
Max
Max
Max
0.0
0−5.5V
0−5.5V
Max
Max
0.0
Max
Max
Max
Max
Max
Conditions
Recognized HIGH Signal
Recognized LOW Signal
IIN = −18 mA
IOH = −3 mA
IOH = −24 mA
IOL = 48 mA
VIN = 2.7V (Note 4)
VIN = VCC
VIN = 7.0V
VIN = 0.5V (Note 4)
VIN = 0.0V
IID = 1.9 µA
All Other Pins Grounded
VOUT = 2.7V; OE = 2.0V
VOUT = 0.5V; OE = 2.0V
VOUT = 0.0V
VOUT = VCC
VOUT = 5.5V; All Others VCC or GND
All Outputs HIGH
All Outputs LOW
OE = VCC; All Others at VCC or GND
VI = VCC − 2.1V
Enable Input VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open
OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
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DC Electrical Characteristics
Symbol
Parameter
Min
Max
Units
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
1.1
-0.45
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW.
V
V
AC Electrical Characteristics
Symbol
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Max Clock
Frequency
Propagation Delay
CP to On
Output Enable Time
Output Disable Time
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
150
1.5 6.9
1.5 6.9
0.8 6.5
1.2 6.5
1.5 9.6
1.5 7.2
Conditions
VCC
CL = 50 pF,
RL = 500
5.0 TA = 25˚C (Note 5)
5.0 TA = 25˚C(Note 5)
Units
MHz
ns
ns
ns
Fig.
No.
Figure 2
Figure 7
Figure 7
AC Operating Requirements
Symbol
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Parameter
Setup Time, HIGH
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Pulse Width, CP
HIGH or LOW
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
1.3
1.3
1.5
1.5
3.3
3.3
Units
ns
ns
ns
Fig.
No.
Figure 6
Figure 6
Figure 5
Capacitance
Symbol
Parameter
Typ
CIN
COUT (Note 6)
Input Capacitance
Output Capacitance
5.0
11.0
Note 6: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
AC Loading
Units
pF
pF
Conditions (TA = 25˚C)
VCC = 0V
VCC = 5.0V
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Amplitude Rep Rate
tW
3.0V
1 MHz 500 ns
tr
2.5 ns
tf
2.5 ns
FIGURE 4. Test Input Signal Requirements
DS100224-6
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100224-7
FIGURE 2. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
DS100224-10
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100224-8
FIGURE 3. Test Input Pulse Requirements
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
DS100224-11
DS100224-12
FIGURE 7. TRI-STATE Output HIGH
and LOW Enable and Disable Times
Book
Extract
End
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PrintDate=1998/07/14 PrintTime=11:05:38 43604 ds100224 Rev. No. 1 cmserv Proof
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