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HY29LV320
32 Mbit (2M x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
n High Performance
– 70, 80, 90 and 120 ns access time
versions for full voltage range operation
n Ultra-low Power Consumption (Typical/
Maximum Values)
– Automatic sleep/standby current: 0.5/5.0
µA
– Read current: 9/16 mA (@ 5 MHz)
– Program/erase current: 20/30 mA
n Top and Bottom Boot Block Versions
– Provide one 8 KW, two 4 KW, one 16 KW
and sixty-three 32 KW sectors
n Secured Sector
– An extra 128-word, factory-lockable
sector available for an Electronic Serial
Number and/or additional secured data
n Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Temporary Sector Unprotect allows
changes in locked sectors
n Fast Program and Erase Times (typicals)
– Sector erase time: 0.5 sec per sector
– Chip erase time: 32 sec
– Word program time: 11 µs
– Accelerated program time per word: 7 µs
n Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Compliant With Common Flash Memory
Interface (CFI) Specification
– Flash device parameters stored directly
on the device
– Allows software driver to identify and use a
variety of current and future Flash products
n Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
Pinout and software compatible with
single-power supply Flash devices
Superior inadvertent write protection
n Data# Polling and Toggle Bits
Provide software confirmation of
completion of program and erase
operations
n Ready/Busy (RY/BY#) Pin
Provides hardware confirmation of
completion of program and erase
operations
n Write Protect Function (WP#/ACC pin)
Allows hardware protection of the first or
last 32 KW of the array, regardless of sector
protect status
n Acceleration Function (WP#/ACC pin)
Provides accelerated program times
n Erase Suspend/Erase Resume
Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
Erase Resume can then be invoked to
complete suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n Space Efficient Packaging
48-pin TSOP and 63-ball FBGA packages
LOGIC DIAGRAM
21
A[20:0]
CE#
OE#
WE#
RESET#
DQ[15:0]
16
WP#/ACC
RY/BY#
Revision 1.3, May 2002

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HY29LV320
GENERAL DESCRIPTION
The HY29LV320 is a 32 Mbit, 3 volt-only CMOS
Flash memory organized as 2,097,152 (2M) words.
The device is available in 48-pin TSOP and 63-
ball FBGA packages. Word-wide data (x16) ap-
pears on DQ[15:0].
The HY29LV320 can be programmed and erased
in-system with a single 3 volt VCC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a higher voltage VPP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as fast as 70ns over
the full operating voltage range of 2.7 - 3.6 volts
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-
cessors. To eliminate bus contention, the
HY29LV320 has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a word at a time
by executing the four-cycle Program Command
write sequence. This initiates an internal algorithm
that automatically times the program pulse widths
and verifies proper cell margin. Faster program-
ming times are achieved by placing the
HY29LV320 in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29LV320 features a sector architecture and
is offered in two versions:
n HY29LV320B - a device with boot-sector archi-
tecture with the boot sectors at the bottom of the
address range, containing one 8KW, two 4KW,
one 16KW and sixty-three 32KW sectors.
n HY29LV320T - a device with boot-sector archi-
tecture with the boot sectors at the top of the
address range, containing one 8KW, two 4KW,
one 16KW and sixty-three 32KW sectors.
The HY29LV320s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
As during programming cycles, the device auto-
matically times the erase pulse widths and veri-
fies proper cell margin. Sectors are arranged into
designated groups for purposes of protection and
unprotection. Sector Group Protection optionally
disables both program and erase operations in any
combination of the sector groups of the memory
array, while Temporary Sector Group Unprotect
allows in-system erasure and code changes in
previously protected sector groups. Erase Sus-
pend enables the user to put erase on hold for
any period of time to read data from, or program
data to, any sector that is not selected for era-
sure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
Hardware data protection measures include a low
VCC detector that automatically inhibits write op-
erations during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The Secured Sector is an extra 128 word sector
capable of being permanently locked at the fac-
tory or by customers. The Secured Indicator Bit
(accessed via the Electronic ID mode) is perma-
nently set to a 1if the part is factory locked, and
permanently set to a 0if customer lockable. This
way, customer lockable parts can never be used
to replace a factory locked part. Factory locked
parts provide several options. The Secured Sec-
tor may store a secure, random 8-word ESN (Elec-
tronic Serial Number), customer code pro-
grammed at the factory, or both. Customer Lock-
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able parts may utilize the Secured Sector as bo-
nus space, reading and writing like any other Flash
sector, or may permanently lock their own code
there.
The WP#/ACC pin provides two functions. The
Write Protect function provides a hardware method
of protecting the boot sectors without using a high
voltage. The Accelerate function speeds up pro-
gramming operations, and is intended primarily to
allow faster manufacturing throughput.
Two power-saving features are embodied in the
HY29LV320. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
HY29LV320
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flex-
ible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary volt-
ages and timing information. This allows one set
of software drivers to identify and use a variety of
different, current and future Flash products. The
standard which details the software interface nec-
essary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29LV320 is fully compliant with this specification.
BLOCK DIAGRAM
A[20:0]
WE#
CE#
OE#
RESET#
RY/BY#
WP#/ACC
STATE
CONTROL
COMMAND
REGISTER
CFI
CONTROL
CFI DATA
MEMORY
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
TIMER
VCC
DETECTOR
A[20:0]
X-DECODER
r1.3/May 02
DQ[15:0]
I/O BUFFERS
DATA LATCH
Y-GATING
32 Mb FLASH
MEMORY
ARRAY
(67 Sectors)
128-word
FLASH
Security Sector
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HY29LV320
SIGNAL DESCRIPTIONS
Name
Type
Description
A[20:0]
Inputs
Address, active High. These 21 inputs select one of 2,097,152 (2M) words
within the array for read or write operations.
DQ[15:0]
Inputs/Outputs Data Bus, active High. These pins provide a 16-bit data path for read and
Tri-state write operations.
CE#
Input
Chip Enable, active Low. This input must be asserted to read data from or
write data to the HY29LV320. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
OE#
Input
Output Enable, active Low. This input must be asserted for read operations
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
WE#
Input
Write Enable, active Low. Controls writing of commands or command
sequences for various device operations. A write operation takes place when
WE# is asserted while CE# is also Low and OE# is High.
RESET#
Input
Hardware Reset, active Low. Provides a hardware method of resetting the
HY29LV320 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted
the device will be in the Standby mode.
RY/BY#
Output
Open Drain
Ready/Busy Status. Indicates whether a write or erase command is in
progress or has been completed. Valid after the rising edge of the final WE#
pulse of a command sequence. Remains Low while the device is actively
programming data or erasing, and goes High when it is ready to read array data.
Write Protect, active Low/Accelerate (VHH).
Placing this pin at VIL disables program and erase operations in the top or bottom
32K words of the array. The affected sectors are sectors S0 - S3 for the
HY29LV320B and sectors S63 - S66 for the HY29LV320T.
If the pin is placed at VIH, the protection state of those two sectors reverts to
whether they were last set to be protected or unprotected using the Sector Group
Protection and Unprotection capability of the HY29LV320.
WP#/ACC
Input
If VHH is applied to this input, the device enters the Unlock Bypass mode,
temporarily unprotects any protected sectors, and uses the higher voltage on the
pin to reduce the time required for program operations. (The system would then
use the two-cycle program command sequence as required by the Unlock
Bypass mode.) Removing VHH from the pin returns the device to normal
operation.
This pin must not be at VHH for operations other than accelerated programming,
or device damage may result. Leaving the pin floating or unconnected may result
in inconsistent device operation.
VIH
Input
High Input. Connect to VIH or to VCC to provide compatibility with similar x8/x16
devices.
VCC -- 3-volt (nominal) power supply.
VSS -- Power and signal ground.
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PIN CONFIGURATIONS
63- B allF B G A - To p V iew , B alls F acing D o w n
HY29LV320
A8 B8
NC NC
L8 M 8
NC NC
A 7 B 7 C 7 D 7 E 7 F7 G 7 H 7 J7 K 7 L7 M 7
N C N C A [13] A [12] A [14] A [15] A [16] V 10 D Q [15] V 55 N C N C
C 6 D 6 E 6 F6 G 6 H 6 J6 K 6
A [9] A [8] A [10] A [11] D Q [7] D Q [14] D Q [13] D Q [6]
C 5 D 5 E 5 F5 G 5 H 5 J5 K 5
W E # R E S E T# N C A [19] D Q [5] D Q [12] V + + D Q [4]
C 4 D 4 E 4 F4 G 4 H 4 J4 K 4
R Y /B Y # W P # /A C C A [18] A [20] D Q [2] D Q [10] D Q [11] D Q [3]
C3 D3 E3
A [7] A [17] A [6]
F3 G 3 H 3 J3 K 3
A [5] D Q [0] D Q [8] D Q [9] D Q [1]
A 2 C 2 D 2 E 2 F2 G 2 H 2 J2 K 2 L2 M 2
NC
A [3] A [4] A [2] A [1] A [0] C E # O E #
V55
NC
NC
A1 B1
L1 M 1
NC NC
NC NC
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[19]
A[20]
WE#
RESET#
NC
WP#/ACC
RY/BY#
A[18]
A[17]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
r1.3/May 02
TSOP48
48 A[16]
47 VIH
46 VSS
45 DQ[15]
44 DQ[7]
43 DQ[14]
42 DQ[6]
41 DQ[13]
40 DQ[5]
39 DQ[12]
38 DQ[4]
37 VCC
36 DQ[11]
35 DQ[3]
34 DQ[10]
33 DQ[2]
32 DQ[9]
31 DQ[1]
30 DQ[8]
29 DQ[0]
28 OE#
27 VSS
26 CE#
25 A[0]
5