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HY29LV800
8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
n High Performance
– 70 and 90 ns access time versions for full
voltage range operation
– 55 ns access time version for operation
from 3.0 to 3.6 volts
n Ultra-low Power Consumption (Typical
Values)
– Automatic sleep mode current: 0.2 µA
– Standby mode current: 0.2 µA
– Read current: 7 mA (at 5 Mhz)
– Program/erase current: 15 mA
n Flexible Sector Architecture:
– One 16 KB, two 8 KB, one 32 KB and
fifteen 64 KB sectors in byte mode
– One 8 KW, two 4 KW, one 16 KW and
fifteen 32 KW sectors in word mode
– Top or bottom boot block configurations
available
n Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Sectors lockable in-system or via
programming equipment
– Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
n Fast Program and Erase Times
– Sector erase time: 0.5 sec typical for each
sector
– Chip erase time: 10 sec typical
– Byte program time: 9 µs typical
– Word program time: 11 µs typical
n Unlock Bypass Program Command
– Reduces programming time when issuing
multiple program command sequences
n Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
Pinout and software compatible with
single-power supply Flash devices
Superior inadvertent write protection
n Data# Polling and Toggle Bits
Provide software confirmation of
completion of program and erase
operations
n Ready/Busy# Pin
Provides hardware confirmation of
completion of program and erase
operations
n Erase Suspend/Erase Resume
Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
Erase Resume can then be invoked to
complete suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n Space Efficient Packaging
44-pin PSOP, 48-pin TSOP and 48-ball
FBGA packages
LOGIC DIAGRAM
19
A[18:0]
DQ[7:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ[15]/A[-1]
RY/BY#
8
7
Preliminary
Revision 1.0, November 2001

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HY29LV800
GENERAL DESCRIPTION
The HY29LV800 is an 8 Mbit, 3 volt-only, CMOS
Flash memory organized as 1,048,576 (1M) bytes
or 524,288 (512K) words that is available in 44-
pin PSOP, 48-pin TSOP and 48-ball FBGA pack-
ages. Word-wide data (x16) appears on DQ[15:0]
and byte-wide (x8) data appears on DQ[7:0].
The HY29LV800 can be programmed and erased
in-system with a single 3 volt VCC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a higher voltage VPP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 70 ns over
the full operating voltage range of 2.7 - 3.6 volts
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-
cessors. A 55 ns version operating from 3.0 to
3.6 volts is also available. To eliminate bus con-
tention, the HY29LV800 has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings. They are
then routed to an internal state-machine that con-
trols the erase and programming circuits. Device
programming is performed a byte/word at a time
by executing the four-cycle Program Command
write sequence. This initiates an internal algorithm
that automatically times the program pulse widths
and verifies proper cell margin. Faster program-
ming times can be achieved by placing the
HY29LV800 in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29LV800s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
As during programming cycles, the device auto-
matically times the erase pulse widths and veri-
fies proper cell margin. Hardware Sector Protec-
tion optionally disables both program and erase
operations in any combination of the sectors of
the memory array, while Temporary Sector Unpro-
tect allows in-system erasure and code changes
in previously protected sectors. Erase Suspend
enables the user to put erase on hold for any pe-
riod of time to read data from, or program data to,
any sector that is not selected for erasure. True
background erase can thus be achieved. The de-
vice is fully erased when shipped from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Hardware data protection measures include a low
VCC detector that automatically inhibits write op-
erations during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Two power-saving features are embodied in the
HY29LV800. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
2 Rev. 1.0/Nov. 01

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BLOCK DIAGRAM
A[18:0], A[-1]
DQ[15:0]
WE#
CE#
OE#
BYTE#
RESET#
RY/BY#
STATE
CONTROL
COMMAND
REGISTER
VCC DETECTOR
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
TIMER
A[18:0], A[-1]
X-DECODER
HY29LV800
DQ[15:0]
I/O BUFFERS
DATA LATCH
Y-GATING
8 Mb FLASH
MEMORY
ARRAY
(19 Sectors)
SIGNAL DESCRIPTIONS
Name
A[18:0]
DQ[15]/A[-1],
DQ[14:0]
BYTE#
CE#
OE#
WE#
RESET#
RY/BY#
VCC
VSS
Type
Description
Inputs
Address, active High. These 19 inputs, combined with the DQ[15]/A[-1] input in
Byte mode, select one location within the array for read or write operations.
Inputs/Outputs
Tri-state
Data Bus, active High. These pins provide an 8- or 16-bit data path for read
and write operations. In Byte mode, DQ[15]/A[-1] is used as the LSB of the 20bit
byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode.
Input
Byte Mode, active Low. Low selects Byte mode, High selects Word mode.
Input
Chip Enable, active Low. This input must be asserted to read data from or
write data to the HY29LV800. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
Input
Output Enable, active Low. Asserted for read operations and negated for
write operations. BYTE# determines whether a byte or a word is read during the
read operation.
Input
Write Enable, active Low. Controls writing of commands or command
sequences in order to program data or erase sectors of the memory array. A write
operation takes place when WE# is asserted while CE# is Low and OE# is High.
Input
Hardware Reset, active Low. Provides a hardware method of resetting the
HY29LV800 to the read array state. When the device is reset, it immediately
terminates any operation in progress. While RESET# is asserted, the device
will be in the Standby mode.
Output
Open Drain
Ready/Busy Status. Indicates whether a write or erase command is in
progress or has been completed. Remains Low while the device is actively
programming data or erasing, and goes High when it is ready to read array data.
-- 3-volt (nominal) power supply.
-- Power and signal ground.
Rev. 1.0/Nov. 01
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HY29LV800
PIN CONFIGURATIONS
48-Ball FBGA (6 x 8 mm, Top View, Balls Facing Down)
A6 B6
A[13]
A[12]
A5 B5
A[9] A[8]
A4 B4
WE# RESET#
A3 B3
RY/BY#
NC
A2 B2
A[7] A[17]
A1 B1
A[3] A[4]
C6
A[14]
C5
A[10]
C4
NC
C3
A[18]
C2
A[6]
C1
A[2]
D6
A[15]
D5
A[11]
D4
NC
D3
NC
D2
A[5]
D1
A[1]
E6
A[16]
E5
DQ[7]
E4
DQ[5]
E3
DQ[2]
E2
DQ[0]
E1
A[0]
F6 G6 H6
BYTE# DQ[15]/A[-1]
F5 G5
VSS
H5
DQ[14] DQ[13]
DQ[6]
F4 G4 H4
DQ[12] VCC DQ[4]
F3 G3 H3
DQ[10] DQ[11]
DQ[3]
F2 G2 H2
DQ[8]
DQ[9]
DQ[1]
F1 G1 H1
CE# OE#
VSS
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard
TSOP48
48 A16
47 BYTE#
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
4 Rev. 1.0/Nov. 01

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CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (VIH) causes assertion of the
signal. A #symbol following the signal name, e.g.,
RESET#, indicates that the signal is asserted in
the Low state (VIL). See DC specifications for VIH
and VIL values.
MEMORY ARRAY ORGANIZATION
The 8 Mbit Flash memory array is organized into
19 blocks called sectors (S0, S1, . . . , S18). A
sector is the smallest unit that can be erased and
that can be protected to prevent accidental or un-
authorized erasure. See the Bus Operationsand
Command Definitionssections of this document
for additional information on these functions.
In the HY29LV800, four of the sectors, which com-
prise the boot block, vary in size from 8 to 32
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 3 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 4.
Read Operation
Data is read from the HY29LV800 by using stan-
dard microprocessor read cycles while placing the
byte or word address on the devices address in-
puts. The host system must drive the CE# and
OE# pins LOW and drive WE# high for a valid read
operation to take place. The BYTE# pin determines
whether the device outputs array data in words
(DQ[15:0]) or in bytes (DQ[7:0]).
The HY29LV800 is automatically set for reading
array data after device power-up and after a hard-
HY29LV800
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
Kbytes (4 to 16 Kwords), while the remaining 15
sectors are uniformly sized at 64 Kbytes (32
Kwords). The boot block can be located at the
bottom of the address range (HY29LV800B) or at
the top of the address range (HY29LV800T).
Tables 1 and 2 define the sector addresses and
corresponding address ranges for the top and bot-
tom boot block versions of the HY29LV800.
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host reads from an address
within an erase-suspended (or erasing) sector, or
while the device is performing a byte or word pro-
gram operation, the device outputs status data
instead of array data. After completing an Auto-
matic Program or Automatic Erase algorithm within
a sector, that sector automatically returns to the
read array data mode. After completing a program-
ming operation in the Erase Suspend mode, the
system may once again read array data with the
same exception noted above.
The host must issue a hardware reset or the soft-
ware reset command to return a sector to the read
array data mode if DQ[5] goes high during a pro-
gram or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
Rev. 1.0/Nov. 01
5