61LV256.pdf 데이터시트 (총 8 페이지) - 파일 다운로드 61LV256 데이타시트 다운로드

No Preview Available !

IS61LV256
IS61LV256
32K x 8 LOW VOLTAGE CMOS STATIC RAM
ISSIISSI®®
FEBRUARY 1996
FEATURES
• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 345 mW (max.) operating
— 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 12 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil DIP and SOJ, plus the 450-mil TSOP package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-1

No Preview Available !

IS61LV256
PIN CONFIGURATION
28-Pin DIP and SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
ISSI®
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
PIN DESCRIPTIONS
A0-A14
CE
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
WE CE OE I/O Operation Vcc Current
Not Selected
(Power-down)
Output Disabled
Read
Write
XHX
HLH
HL L
LLX
High-Z
High-Z
DOUT
DIN
ISB1, ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2-2 Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61

No Preview Available !

IS61LV256
ISSI®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V +10%, –5%
3.3V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
ILI Input Leakage
ILO Output Leakage
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
GND VIN VCC
GND VOUT VCC, Outputs Disabled
Com.
Ind.
Com.
Ind.
Min.
2.4
2.2
–0.3
–2
–5
–2
–5
Max.
0.4
VCC + 0.3
0.8
2
5
2
5
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
ICC1 Vcc Operating
Supply Current
ICC2 Vcc Dynamic Operating
Supply Current
ISB1 TTL Standby Current
(TTL Inputs)
ISB2 CMOS Standby
Current (CMOS Inputs)
Test Conditions
VCC = Max., CE = VIL
IOUT = 0 mA, f = 0
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CE VIH, f = 0
VCC = Max.,
CE VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN 0.2V, f = 0
-12 ns
Min. Max.
Com. — 50
Ind. — —
Com. — 100
Ind. — —
Com. — 10
Ind. — —
Com. — 2
Ind. — —
-15 ns
Min. Max.
— 50
— 60
— 90
— 100
— 10
— 20
—2
—5
-20 ns
Min. Max.
— 50
— 60
— 80
— 90
— 10
— 20
—2
—5
-25 ns
Min. Max.
— 50
— 60
— 70
— 80
— 10
— 20
—2
—5
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
mA
mA
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
5
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-3

No Preview Available !

IS61LV256
ISSI®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA
tACE
tDOE
tLZOE(2)
tHZOE(2)
tLZCE(2)
tHZCE(2)
tPU(3)
tPD(3)
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
CE to Power-Down
-12 ns
Min. Max.
12 —
— 12
2—
— 12
—6
0—
—7
3—
—5
0—
— 13
-15 ns
Min. Max.
15 —
— 15
2—
— 15
—7
0—
—8
3—
—6
0—
— 15
-20 ns
Min. Max.
20 —
— 20
2—
— 20
—8
0—
—9
3—
—9
0—
— 18
-25 ns
Min. Max.
25 —
— 25
2—
— 25
—9
0—
— 10
3—
— 10
0—
— 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
3.3V
635
OUTPUT
30 pF
Including
jig and
scope
702
Figure 1a.
3.3V
635
OUTPUT
5 pF
Including
jig and
scope
702
Figure 1b.
2-4 Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61

No Preview Available !

IS61LV256
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
ADDRESS
DOUT
ISSI®
tRC
tOHA
tAA
tOHA
DATA VALID
READ CYCLE NO. 2(1,3)
ADDRESS
OE
CE
DOUT
SUPPLY
CURRENT
tRC
tAA
tACE
tLZCE
HIGH-Z
tDOE
tLZOE
tPU
50%
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
tOHA
tHZOE
tHZCE
DATA VALID
tPD
50%
ICC
ISB
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-5