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IS61LV5128
ISSI®
512K x 8 HIGH-SPEED CMOS STATIC RAM
JULY 2001
FEATURES
• High-speed access times:
10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
DESCRIPTION
The ISSI IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The IS61LV5128
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128 is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
VCC
GND
I/O0-I/O7
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
1

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IS61LV5128
PIN CONFIGURATION
36 mini BGA
1 23 45 6
A A0 A1 NC A3 A6 A8
B I/O4 A2 WE A4 A7 I/O0
C I/O5
NC A5
I/O1
D GND
Vcc
E Vcc
GND
F I/O6
A18 A17
I/O2
G I/O7 OE CE A16 A15 I/O3
H A9 A10 A11 A12 A13 A14
44-Pin TSOP (Type II)
NC 1
NC 2
A0 3
A1 4
A2 5
A3 6
A4 7
CE 8
I/O0 9
I/O1 10
Vcc 11
GND 12
I/O2 13
I/O3 14
WE 15
A5 16
A6 17
A7 18
A8 19
A9 20
NC 21
NC 22
ISSI ®
44 NC
43 NC
42 NC
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/O7
35 I/O6
34 GND
33 Vcc
32 I/O5
31 I/O4
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
PIN DESCRIPTIONS
A0-A18
CE
OE
WE
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vcc Power
GND
Ground
NC No Connection
TRUTH TABLE
Mode
WE
Not Selected X
(Power-down)
Output Disabled H
Read
H
Write
L
CE OE I/O Operation Vcc Current
HX
High-Z
ISB1, ISB2
LH
LL
LX
High-Z
DOUT
DIN
ICC
ICC
ICC
36-Pin SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 Vcc
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
2 Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
07/16/01

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IS61LV5128
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 V
TBIAS
Temperature Under Bias
55 to +125
°C
TSTG
Storage Temperature
65 to +150
°C
PT Power Dissipation
1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ISSI ®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
10 ns
VCC
3.3V +10%, -5%
3.3V +10%, -5%
12 ns, 15 ns
VCC
3.3V ± 10%
3.3V ± 10%
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
CIN Input Capacitance
VIN = 0V
6
CI/O
Input/Output Capacitance
VOUT = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Unit
pF
pF
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
07/16/01
3

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IS61LV5128
ISSI ®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
ILI Input Leakage
Test Conditions
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
GND VIN VCC
ILO Output Leakage
GND VOUT VCC, Outputs Disabled
Note:
1. VIL = 3.0V for pulse width less than 10 ns.
Com.
Ind.
Com.
Ind.
Min.
2.4
2.0
0.3
1
5
1
5
Max.
0.4
VCC + 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
ICC Vcc Operating VCC = Max., CE = VIL
Supply Current IOUT = 0 mA, f = fMAX.
Com.
Ind.
145
155
135
145
125
135
ISB TTL Standby VCC = Max.,
Current
VIN = VIH or VIL
(TTL Inputs)
CE VIH, f = fMAX.
Com.
Ind.
70
80
60
70
50
60
ISB1 TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE VIH, f = 0
Com.
Ind.
20
25
20
25
20
25
ISB2 CMOS Standby VCC = Max.,
Current
CE VCC 0.2V,
(CMOS Inputs) VIN VCC 0.2V, or
VIN 0.2V, f = 0
Com.
Ind.
10
15
10
15
10
15
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
mA
mA
4 Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
07/16/01

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IS61LV5128
ISSI ®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
tRC Read Cycle Time
10
12
15
ns
tAA
Address Access Time
10
12
15
ns
tOHA Output Hold Time
3
3
3
ns
tACE CE Access Time
10
12
15
ns
tDOE OE Access Time
4
5
7
ns
tLZOE(2)
OE to Low-Z Output
0
0
0
ns
tHZOE(2)
OE to High-Z Output
04
05
06
ns
tLZCE(2)
CE to Low-Z Output
3
3
3
ns
tHZCE(2)
CE to High-Z Output
04
06
08
ns
tPU Power Up Time
0
0
0
ns
tPD Power Down Time
10
12
15
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
319
OUTPUT
30 pF
Including
jig and
scope
353
3.3V
319
OUTPUT
5 pF
Including
jig and
scope
353
Figure 1
Figure 2
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. B
07/16/01
5