61S6432.pdf 데이터시트 (총 19 페이지) - 파일 다운로드 61S6432 데이타시트 다운로드

No Preview Available !

IS61S6432
ISSI®
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
JUNE 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ISSI IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GNDQ, on MODE pin selects
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.
FAST ACCESS TIME
Symbol Parameter
-200(1)
tKQ CLK Access Time 4
tKC Cycle Time
5
— Frequency
200
Note:
1. ADVANCE INFORMATION ONLY.
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7 -8 Unit
7 8 ns
13 15 ns
75 66 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
1

No Preview Available !

IS61S6432
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
A15-A0
16
GW
BWE
BW4
BW3
BW2
BW1
CE1
CE2
CE3
OE
PB
ISSI ®
MODE
CLK
Q0
BINARY
COUNTER
CE Q1
A0
A1
CLR
A0'
A1'
DQ
ADDRESS
REGISTER
CE
CLK
14 16
64K x 32
MEMORY
ARRAY
32 32
DQ
DQ32-DQ25
BYTE WRITE
REGISTERS
CLK
DQ
DQ24-DQ17
BYTE WRITE
REGISTERS
CLK
DQ
DQ16-DQ9
BYTE WRITE
REGISTERS
CLK
DQ
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
DQ
ENABLE
REGISTER
CE
CLK
DQ
ENABLE
DELAY
REGISTER
CLK
4
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32
OE
DATA[32:1]
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01

No Preview Available !

IS61S6432
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
ISSI ®
PIN DESCRIPTIONS
A0-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
GW
CE1, CE2, CE3
Address Inputs
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
OE
DQ1-DQ32
ZZ
MODE
VCC
GND
VCCQ
GNDQ
NC
Output Enable
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Isolated Output Buffer Ground
No Connect
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01
3

No Preview Available !

IS61S6432
ISSI ®
TRUTH TABLE
Operation
Address
Used
CE1 CE2 CE3 ADSP ADSC ADV WRITE OE
DQ
Deselected, Power-down
None
H X X X L X X X High-Z
Deselected, Power-down
None
L L X L X X X X High-Z
Deselected, Power-down
None
L X H L X X X X High-Z
Deselected, Power-down
None
L L X H L X X X High-Z
Deselected, Power-down
None
L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst
External L H L L X X X H High-Z
Write Cycle, Begin Burst
External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst
External L H L H L X H H High-Z
Read Cycle, Continue Burst Next
XX X H H L H L Q
Read Cycle, Continue Burst Next
X X X H H L H H High-Z
Read Cycle, Continue Burst Next
HX X X H L H L Q
Read Cycle, Continue Burst Next
H X X X H L H H High-Z
Write Cycle, Continue Burst Next
XX X H HL
L XD
Write Cycle, Continue Burst Next
HX X X H L L X D
Read Cycle, Suspend Burst Current X X X H H H H L Q
Read Cycle, Suspend Burst Current X X X H H H H H High-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X H H H H High-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
GW BWE BW1 BW2 BW3 BW4
H H X X XX
H X H H HH
H L L H HH
X L L L LL
L X X X XX
PB Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01

No Preview Available !

IS61S6432
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
ISSI ®
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1,2,3)
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under Bias
40 to +85
°C
TSTG
Storage Temperature
55 to +150
°C
PD Power Dissipation
1.8 W
IOUT Output Current (per I/O)
100 mA
VIN, VOUT
Voltage Relative to GND for I/O Pins
0.5 to VCCQ + 0.3
V
VIN
Voltage Relative to GND for for Address and Control Inputs
0.5 to 5.5
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
VCC
3.3V +10%, 5%
3.3V +10%, 5%
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01
5