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IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
ISSI ®
JANUARY 2004
FEATURES
• Fast access time:
– 117, 100 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VDDQ to alter their power-up state
DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the i486™, Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with ISSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1
controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/
O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/
O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GNDQ, on MODE pin
selects LINEAR Burst. A VDDQ (or no connect) on MODE pin
selects INTERLEAVED Burst.
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
1

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IS61SP6464
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
A15-A0
16
GW
BWE
BW8
MODE
CLK Q0
BINARY
COUNTER
CE Q1
A0
A1
CLR
A0'
A1'
DQ
ADDRESS
REGISTER
CE
CLK
14 16
64K x 64
MEMORY
ARRAY
64 64
DQ
DQ57-DQ64
BYTE WRITE
REGISTERS
CLK
ISSI®
BW1
CE
CE2
CE2
CE3
CE3
OE
2
DQ
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
DQ
ENABLE
REGISTER
CE
CLK
DQ
ENABLE
DELAY
REGISTER
CLK
8
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
64
OE
DATA[64:1]
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04

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IS61SP6464
PIN CONFIGURATION
128-Pin TQFP/PQFP
GNDQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
GNDQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
GNDQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ISSI®
102 VDDQ
101 I/O32
100 I/O31
99 I/O30
98 I/O29
97 I/O28
96 I/O27
95 I/O26
94 I/O25
93 I/O24
92 I/O23
91 I/O22
90 GNDQ
89 VDDQ
88 I/O21
87 I/O20
86 I/O19
85 I/O18
84 I/O17
83 I/O16
82 I/O15
81 I/O14
80 I/O13
79 I/O12
78 GNDQ
77 VDDQ
76 I/O11
75 I/O10
74 I/O9
73 I/O8
72 I/O7
71 I/O6
70 I/O5
69 I/O4
68 I/O3
67 I/O2
66 I/O1
65 GNDQ
PIN DESCRIPTIONS
A0-A15
Address Inputs
CLK
ADSP
ADSC
ADV
BW1-BW8
BWE
GW
CE, CE2, CE2,
CE3, CE3
OE
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
I/O1-I/O64
ZZ
MODE
VDD
GND
VDDQ
NC
GNDQ
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V
No Connect
Isolated Output Buffer Ground
3

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IS61SP6464
ISSI®
TRUTH TABLE
OPERATION
ADDRESS
USED CE3 CE2 CE3 CE2 CE ADSP ADSC ADV WRITE OE CLK I/O
Deselected, Power-down
None X X X X H X L X X X L-H High-Z
Deselected, Power-down
None L X X X L L X X X X L-H High-Z
Deselected, Power-down
None X L X X L L X X X X L-H High-Z
Deselected, Power-down
None X X H X L L X X X X L-H High-Z
Deselected, Power-down
None X X X H L L X X X X L-H High-Z
Deselected, Power-down
None L X X X L H L X X X L-H High-Z
Deselected, Power-down
None X L X X L H L X X X L-H High-Z
Deselected, Power-down
None X X H X L H L X X X L-H High-Z
Deselected, Power-down
None X X X H L H L X X X L-H High-Z
Read Cycle, Begin Burst
External H H L
LL
LXXX
L L-H Dout
Read Cycle, Begin Burst
External H H L L L L X X X H L-H High-Z
Write Cycle, Begin Burst
External H H L
LLHLX
L X L-H Din
Read Cycle, Begin Burst
External H H L
L L H L X H L L-H Dout
Read Cycle, Begin Burst
External H H L
L L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X X X H H L H L L-H Dout
Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z
Read Cycle, Continue Burst
Next
X
X
X
XH
X
H
L
H
L L-H Dout
Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din
Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din
Read Cycle, Suspend Burst Current X X X X X H H H H L L-H Dout
Read Cycle, Suspend Burst Current X X X X X H H H H H L-H High-Z
Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout
Read Cycle, Suspend Burst Current X X X X H X H H H H L-H High-Z
Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din
Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04

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IS61SP6464
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
Pipelined Read
Pipelined Read
Write
Write
L
L
L
L
Deselect
L
Sleep
H
OE
L
H
L
H
X
X
I/O STATUS
Dout
High-Z
High-Z
Din
High-Z
High-Z
ISSI®
WRITE TRUTH TABLE
Operation
GW
Read
Read
Write all bytes
Write all bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Write Byte 5
Write Byte 6
Write Byte 7
Write Byte 8
H
H
H
L
H
H
H
H
H
H
H
H
BWE
H
L
L
X
L
L
L
L
L
L
L
L
BW8
X
H
L
X
H
H
H
H
H
H
H
L
BW7
X
H
L
X
H
H
H
H
H
H
L
H
BW6
X
H
L
X
H
H
H
H
H
L
H
H
BW5
X
H
L
X
H
H
H
H
L
H
H
H
BW4
X
H
L
X
H
H
H
L
H
H
H
H
BW3
X
H
L
X
H
H
L
H
H
H
H
H
BW2
X
H
L
X
H
L
H
H
H
H
H
H
BW1
X
H
L
X
L
H
H
H
H
H
H
H
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
5