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®
Data Sheet
December 2003
ISL6563
FN9126.2
Two-Phase Multi-Phase Buck PWM
Controller with Integrated MOSFET
Drivers
The ISL6563 two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. Multi-phase power conversion is a marked
departure from single phase converter configurations
employed to satisfy the increasing current demands of
modern microprocessors and other electronic circuits. By
distributing the power and load current, implementation of
multi-phase converters utilize smaller and lower cost
transistors with fewer input and output capacitors. These
reductions accrue from the higher effective conversion
frequency with higher frequency ripple current due to the
phase interleaving process of this topology.
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD’s Hammer microprocessors, along
with a system regulation accuracy of ±1%. The droop
characteristic, used to reduce the overshoot or undershoot
of the output voltage, is easily programmed with a single
resistor.
Important features of this controller IC include a set of
sophisticated over-voltage and over-current protection.
Over-voltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the microprocessor. Like other Intersil multiphase
controllers, the ISL6563 uses cost and space-saving
rDS(ON) sensing for channel current balance, dynamic
voltage positioning, and over-current protection. Channel
current balancing is automatic and accurate with the
integrated current-balance control system. Over-current
protection can be tailored to any application with no need for
additional parts. These features provide advanced protection
for the microprocessor and power system.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6563CR-T
0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6563IR-T
0 to 70 24 Ld 4x4 QFN L24.4x4B
ISL6563EVAL1 Evaluation Platform
Features
• Integrated Two-Phase Power Conversion
• Both 5V and 12V Conversion
• Precision Channel Current Sharing
- Loss-Less Current Sampling - Uses rDS(ON)
• Precision Output Voltage Regulation
- ±1% System Accuracy Over Temperature (Commercial)
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD’s
Hammer DAC codes
- Resistor-Programmable Droop Voltage
• Fast Transient Recovery Time
• Over-Current Protection
• Improved, Multi-tiered Over-Voltage Protection
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Pinout
ISL6563 (QFN)
TOP VIEW
24 23 22 21 20 19
VID1 1
18 PHASE1
VID0 2
17 LGATE1
DACSEL/VID5 3
VRM10 4
25
GND
16 PVCC
15 LGATE2
COMP 5
14 PGND
FB 6
13 PHASE2
7 8 9 10 11 12
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
1.65V/1.95V +
-
OVP WHILE
DISABLED
COMP
VID0
VID1
VID2
VID3
VID4
DACSEL/VID5
VRM10
+
200mV
-
OVP
TTL D/A
CONVERTER
(VID DAC)
EA
+
-
OC
FB
GND
DROOP
SOURCE
Σ
OFFSET
SOURCE
Σ
2
SSEND
ENLL VCC PVCC
OSCILLATOR
POWER-ON
RESET (POR)
GATE
CONTROL
SOFT-START
AND
FAULT LOGIC
Σ
Σ
CURRENT
CORRECTION
PWM1
PWM2
CONTROL
LOGIC
GATE
CONTROL
OFS
ISEN
BOOT1
UGATE1
PHASE1
LGATE1
PGND
BOOT2
UGATE2
PHASE2
LGATE2

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Simplified Power System Diagram
+5VIN
ISL6563
5-6
VID
DAC
CHANNEL1
ISL6563
CHANNEL2
Q1
Q2
Q3
Q4
VOUT
Typical Application
+12VIN
+5VIN
CF1
DACSEL/VID12
VID4
VID3
VID2
VID1
VID0
VRM10
RISEN
ISEN
R’OFS
ROFS
SSEND
ENLL
OFS
VCC
LIN
CF2
CHFIN1
PVCC
BOOT1
CBOOT1
UGATE1
Q1
PHASE1
CBIN1
LOUT1
ISL6563
LGATE1
Q2
BOOT2
UGATE2
CBOOT2
CHFIN2
Q3
CBIN2
COMP
C2
C1
R2
FB
R1
PHASE2
LGATE2
PGND
GND
LOUT2
Q4
CHFOUT
VOUT
CBOUT
3

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ISL6563
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Absolute Boot Voltage, VBOOT . . . . . PGND - 0.3V to PGND + 27V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V
Lower Gate Voltage, VLGATE . . . . . . . PGND - 0.3V to VCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . HBM Class 1 JEDEC STD
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
QFN Package (Notes 1, 2). . . . . . . . . .
43
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Recommended Operating Conditions
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VCC = 5V, TJ = 0oC to 85oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
VCC POR (Power-On Reset) Threshold
IVCC; ENLL = high
VCC Rising
- 4 6 mA
4.2 4.4 4.6 V
VCC Falling
3.7 3.9 4.1 V
PVCC POR (Power-On Reset) Threshold
PVCC Rising
- 4.2 - V
Switching Frequency (per channel)
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
PVCC Falling
TJ = 25oC to 85oC
TJ = -40oC
VPP
- 3.3 - V
195 230 265 kHz
183 216 248 kHz
- 1.33 - V
- 66 - %
CONTROL THRESHOLDS
ENLL Rising Threshold
- 0.61 - V
ENLL Hysteresis (Note 3)
- 60 - mV
COMP Shutdown Threshold
0.23 0.36 0.49 V
COMP Shutdown Maximum Pull-Down Impedance
- - 15
REFERENCE AND DAC
System Accuracy
DAC Input Low Voltage
TJ = -40oC to 85oC
-1 -
-1.5 -
--
1%
1.5 %
0.4 V
DAC Input High Voltage
0.8 -
-V
DAC Input Pull-Up Current
VIDx = 0V
- 45 - µA
ERROR AMPLIFIER
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
RL = 10K to ground
CL = 100pF, RL = 10K to ground
CL = 100pF, Load = ±400µA
Load = 1mA
- 96
- 20
-8
3.90 4.20
- dB
- MHz
- V/µs
-V
Minimum Output Voltage
Load = -1mA
- 0.80 0.90 V
4

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ISL6563
Electrical Specifications Test Conditions: VCC = 5V, TJ = 0oC to 85oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP
OVER-CURRENT PROTECTION
Over-Current Trip Level
- 95
PROTECTION
Over-Voltage Threshold while IC Disabled
VRM9.0 configuration
1.90 1.95
Hammer and VRM10.0 configurations
1.60 1.65
Over-Voltage Threshold
FB Rising
- VID
+200mV
Over-Voltage Hysteresis
- 100
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-overlap (Note 3)
LGATE Turn-On Non-overlap (Note 3)
OUTPUT
tRUGATE; VVCC = 5V, 3nF Load
tRLGATE; VVCC = 5V, 3nF Load
tFUGATE; VVCC = 5V, 3nF Load
tFLGATE; VVCC = 5V, 3nF Load
tPDHUGATE; VVCC = 5V, 3nF Load
tPDHLGATE; VVCC = 5V, 3nF Load
-8
-8
-8
-4
-8
-8
Upper Drive Source Resistance
100mA Source Current
- 0.5
Upper Drive Sink Resistance
100mA Sink Current
- 0.4
Lower Drive Source Resistance
100mA Source Current
0.5
Lower Drive Sink Resistance
100mA Sink Current
- 0.3
NOTE:
3. Parameter magnitude guaranteed by design.
MAX UNITS
- µA
2.00 V
1.70 V
-V
- mV
- ns
- ns
- ns
- ns
- ns
- ns
1.3
1.0
1.3
1.0
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tPDHLGATE
tRLGATE
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1µF
ceramic capacitor.
5
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1µF
ceramic capacitor.
GND and PGND (Pins 25 and 14)
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.