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®
PRELIMINARY
Data Sheet
ISL6565A, ISL6565B
December 2003
FN9135
Multi-Phase PWM Controller with
Precision rDS(ON) or DCR Current Sensing
for VR10.X Application
The ISL6565A, ISL6565B controls microprocessor core
voltage regulation by driving up to 3 synchronous-rectified
buck channels in parallel. Multi-phase buck converter
architecture uses interleaved timing to multiply channel
ripple frequency and reduce input and output ripple currents.
The difference between the ISL6565A and the ISL6565B is
that the ISL6565A utilizes rDS(ON) current sensing, while the
ISL6565B utilizes DCR current sensing for each phase.
These cost and space saving methods of current sensing
are used for adaptive voltage positioning (droop), channel-
current balancing, and over-current protection. To ensure
the accuracy of droop, a programmable internal temperature
compensation function is implemented to compensate the
effect of rDS(ON) and DCR temperature sensitivity.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds is eliminated using the remote-sense
amplifier. The precision threshold-sensitive enable input is
available to accurately coordinate the start up of the
ISL6565A, ISL6565B with Intersil MOSFET driver ICs.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6565ACB
0 to 105 28 Ld SOIC
ISL6565ACR
0 to 105 28 Ld 5x5 QFN
ISL6565ACV
0 to 105 28 Ld TSSOP
ISL6565BCB
0 to 105 28 Ld SOIC
ISL6565BCR
0 to 105 28 Ld 5x5 QFN
ISL6565BCV
0 to 105 28 Ld TSSOP
PKG. DWG. #
M28.3
L28.5x5
M28.173
M28.3
L28.5x5
M28.173
Features
• Multi-Phase Power Conversion
- 2 or 3 Phase Operation
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature and Life
- Adjustable Reference-Voltage Offset
• Precision rDS(ON) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Low-Cost, Lossless Current Sensing
• Input Voltage: 12V or 5V Bias
• Microprocessor Voltage Identification Input
- Dynamic VID® Technology
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
• Threshold Enable Function for Precision Sequencing
• Over Current Protection
• Over-Voltage Protection
• Digital Soft Start
• Operation Frequency up to 1.5MHz per Phase
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Dynamic VID® is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.

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ISL6565A, ISL6565B
Pinouts
ISL6565ACB (SOIC), ISL6565ACV (TSSOP)
TOP VIEW
OVP 1
PGOOD 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
VID12.5 8
OFS 9
TCOMP 10
REF 11
FB 12
COMP 13
VDIFF 14
28 FS
27 EN
26 VCC
25 ENLL
24 NC
23 ISEN2
22 PWM2
21 PWM1
20 ISEN1
19 ISEN3
18 PWM3
17 GND
16 RGND
15 VSEN
ISL6565ACR (QFN)
TOP VIEW
28 27 26 25 24 23 22
VID3 1
21 NC
VID2 2
20 ISEN2
VID1 3
19 PWM2
VID0 4
18 PWM1
VID12.5 5
17 ISEN1
OFS 6
16 ISEN3
TCOMP 7
15 PWM3
8 9 10 11 12 13 14
ISL6565BCB (SOIC), ISL6565BCV (TSSOP)
TOP VIEW
OVP 1
PGOOD 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
VID12.5 8
OFS 9
TCOMP 10
REF 11
FB 12
COMP 13
VDIFF 14
28 FS
27 EN
26 VCC
25 ENLL
24 ICOMMON
23 ISEN2
22 PWM2
21 PWM1
20 ISEN1
19 ISEN3
18 PWM3
17 GND
16 RGND
15 VSEN
ISL6565BCR (QFN)
TOP VIEW
28 27 26 25 24 23 22
VID3 1
21 ICOMMON
VID2 2
20 ISEN2
VID1 3
19 PWM2
VID0 4
18 PWM1
VID12.5 5
17 ISEN1
OFS 6
16 ISEN3
TCOMP 7
15 PWM3
8 9 10 11 12 13 14
2

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ISL6565A Block Diagram
ISL6565A, ISL6565B
VDIFF PGOOD
OVP
VCC
ENLL
RGND
VSEN
x1
S OVP R
LATCH
Q
SHUNT
REGULATOR
POWER-ON
RESET
UVP
OVP
SOFT START
AND
FAULT LOGIC
CLOCK AND
SAWTOOTH
GENERATOR
1.24V
EN
FS
VID4
VID3
VID2
VID1
VID0
VID12.5
REF
FB
COMP
OFS
TCOMP
+200mV
x 0.75
PWM
PWM1
DYNAMIC
VID
D/A
OFFSET
TEMP
COMP
PWM
PWM
E/A
I_TRIP
OC
CHANNEL
CURRENT
BALANCE
I_AVG
1
N
CHANNEL
OCP
PWM2
PWM3
CHANNEL
DETECT
CHANNEL
CURRENT
SENSE
ISEN1
ISEN2
ISEN3
GND
NC
3

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ISL6565B Block Diagram
ISL6565A, ISL6565B
VDIFF PGOOD
OVP
VCC
ENLL
RGND
VSEN
x1
S OVP R
LATCH
Q
SHUNT
REGULATOR
POWER-ON
RESET
UVP
OVP
SOFT START
AND
FAULT LOGIC
CLOCK AND
SAWTOOTH
GENERATOR
1.24V
EN
FS
VID4
VID3
VID2
VID1
VID0
VID12.5
REF
FB
COMP
OFS
TCOMP
+200mV
x 0.75
PWM
PWM1
DYNAMIC
VID
D/A
OFFSET
TEMP
COMP
PWM
PWM
E/A
I_TRIP
OC
CHANNEL
CURRENT
BALANCE
I_AVG
1
N
CHANNEL
OCP
PWM2
PWM3
CHANNEL
DETECT
CHANNEL
CURRENT
SENSE
ISEN1
ISEN2
ISEN3
ICOMMON
GND
4

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Typical Application - ISL6565A
ISL6565A, ISL6565B
+5V
FB COMP VCC
VDIFF
VSEN
RGND
TCOMP
PGOOD
OVP
REF
ISL6565A
VID4
PWM1
VID3
ISEN1
VID2
VID1
PWM2
ISEN2
VID0
VID12.5
PWM3
ISEN3
OFS
FS
GND ENLL
RT
NC
EN
+12V
VID_PGOOD
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
+5V
VCC
EN
BOOT
UGATE
PHASE
ISL6605
PWM LGATE
GND
VIN
VIN
VIN
µP
LOAD
5