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®
Data Sheet
November 2003
ISL6569A
FN9092.1
Multi-Phase PWM Controller
The ISL6569A provides core-voltage regulation by driving
two interleaved synchronous-rectified buck-converter
channels in parallel. Interleaving the channel timing results
in increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6569A uses cost and space-saving rDS(ON) sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The reference and amplifiers are trimmed to ensure
a system accuracy of ± 0.5% over temperature.
Outstanding features of this controller IC include
Dynamic VIDTM technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on VIN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
Features
• Multi-Phase Power Conversion
- 2 Phase Operation
• Active Channel Current Balancing
• Precision rDS(ON) Current Sharing
- Lossless
- Low Cost
• Input Voltage: 12V or 5V Bias
• Precision CORE Voltage Regulation
- ± 0.5% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VIDTM Technology
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 2MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. #
ISL6569ACB
0 to 70 24 Ld SOIC M24.3
ISL6569ACB-T 24 Ld SOIC Tape and Reel
ISL6569ACR
0 to 85 32 Ld 5x5 QFN L32.5x5
ISL6569ACR-T 32 Ld 5x5 QFN Tape and Reel
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6569ACB (24 LD SOIC)
TOP VIEW
GND 1
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
24 EN
23 FS/DIS
22 PGOOD
21 ISEN1
20 PWM1
19 PWM2
18 GND
17 ISEN2
16 VCC
15 GND
14 RGND
13 VSEN
ISL6569A
ISL6569ACR (32 LD 5x5 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
VID2 1
24 NC
VID1 2
23 NC
VID0 3
22 ISEN1
NC 4
21 PWM1
OFS 5
20 PWM2
COMP 6
19 GND
FB 7
18 ISEN2
NC 8
17 NC
9 10 11 12 13 14 15 16
2

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Block Diagram
PGOOD
VID4
VID3
VID2
VID1
VID0
DYNAMIC
VID
DAC
UV
FB
COMP
e/a
ISL6569A
VCC
EN
1.23V
FS
6V
POR
AND
SOFT START
OSCILLAT0R
AND
SAWTOOTH
+
+
-
+
-
+
OFS
VDIFF
VSEN
RGND
IDROOP
x0.1
100µA
OV
2.2V
90µA
diff
OC
AVERAGE
1/2
+
+
I1
CURRENT
SENSE
I2
PWM1
PWM2
OVP
ISEN1
ISEN2
GND
3

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ISL6569A
Typical Application - 2 Phase Converter
+12V
+12V
300
RGND VSEN
VDIFF
VCC
FB
IOUT
PWM1
ISEN1
+12V
PVCC
VCC
BOOT
UGATE
PWM
DRIVER
HIP6601B
PHASE
LGATE
GND
COMP
OFS ISL6569A
FS/DIS
VID4
VID3
VID2
VID1
VID0
PGOOD
EN
GND
PWM2
ISEN2
+12V
PVCC
BOOT
VCC
RT
UGATE
PHASE
DRIVER
HIP6601B
LGATE
PWM
GND
+12V
RISEN1
+12V
VOUT
µP
LOAD
RISEN2
4

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ISL6569A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage. . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3kV
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . .
63
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0o C to 70oC. Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
SHUNT REGULATOR
VCC Voltage
VCC Sink Current
POWER-ON RESET AND ENABLE
VCC = 5VDC; EN = 5VDC; RT = 100 k±1%
VCC = 5VDC; EN = 0VDC; RT = 100 k±1%
VCC tied to 12VDC thru 300resistor, RT = 100k
VCC tied to 12VDC thru 300resistor, RT = 100k
8.0 10.8 14.0 mA
8.0 10.3 13.0 mA
5.63 5.8 5.97 V
15 20 25 mA
POR Threshold
VCC Rising
4.25 4.35 4.50 V
VCC Falling
3.75 3.85 4.00 V
ENABLE Threshold
EN Rising
1.205 1.23 1.255 V
Hysteresis
86 92 98 mV
REFERENCE VOLTAGE AND DAC
Reference Voltage
0.792 0.8 0.808 V
System Accuracy
VID on Fly Step Size
VID Pull Up
(Note 4)
RT = 100k
-0.5 -
- 25
- -20
0.5 %VID
- mV
- µA
VID Input Low Level
VID Input High Level
- 0.8
- 1.36 1.6
V
V
PIN-ADJUSTABLE OFFSET
OFS Current
- 100 -
µA
Offset Accuracy
ROFS = 5.00k±1%
47.0 50.0 53.0 mV
OSCILLATOR
Accuracy
-10 - 10 %
Adjustment Range
0.08 -
1.0 MHz
5