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®
Data Sheet
September 2003
ISL6580
FN9060.2
Integrated Power Stage
Processors that operate above 1GHz require fast, intelligent
power systems. The ISL6580 Integrated Power Stage is a
High Side FET/driver combination that provides high current
capability per converter phase at high switching frequency.
The chip incorporates intelligence to provide fast transient
response and digital communication to the ISL6590 Digital
Controller. The ISL6580 integrates key power stage
components for fast power delivery, effective thermal design
and increased noise immunity. It incorporates an integrated
P-channel high side MOSFET, high side MOSFET driver
and a driver for external synchronous rectifier, low side
MOSFETs. The ISL6580 also features a window comparator
for fast transient response as well as on-board voltage and
current A/D converters for intelligent digital communication
and control by the ISL6590 Controller.
Furthermore, through the communication bus, configuration
and fault monitoring via the ISL6590 are available.
For more information, see the ISL6590 datasheet.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
DWG. #
ISL6580CR
0 to 70
56 Ld 8x8 QFN L56.8x8C
ISL6580CR-T
56 Ld QFN Tape & Reel
ISL6580/90EVAL1 Evaluation Board
ISL6580/90EVAL2 Evaluation Board
ISL6580/90EVAL3 Evaluation Board
Pinout
ISL6580 (QFN)
TOP VIEW
SDATA 1
PWM 2
NDRIVE 3
GND 4
VSW 5
VSW 6
VSW 7
VSW 8
VSW 9
VSW 10
VSW 11
GND 12
GND 13
VDRIVE 14
VCC
42 SOC
41 IS_PLUS
40 IS_MINUS
39 GND
38 VSW
37 VSW
36 VSW
35 VSW
34 VSW
33 VSW
32 VSW
31 GND
30 GND
29 VDRIVE
Features
• Optimized for Intel VR10 applications
• VIN = 12V
• Phase switching frequencies of 250kHz to 1MHz
• Phase current capability up to 25A
• High Side P-channel MOSFET
• Low Side MOSFET drivers
• Accurate, lossless, Current Sense
• Programmable MOSFET non-overlap timing (through the
ISL6590 Digital Controller)
• Active Transient Response (ATR) minimizes voltage
droop/overshoot during large load current transients.
• Serial control interface for system monitoring and
configuration (with ISL6590 Controller)
- Input Under Voltage Protection
- Output Under/Over Voltage Protection
- Peak Current Limit
- Thermal Shutdown
- ATR Limits
• Provides an optimal power solution when combined with
the ISL6590 Digital Controller
- Output voltage regulation range of 0.3VDC to 1.85VDC
- VRM-9 and VRM-10 VID Codes
• Digital interface for high noise immunity and point-of-load
placement
• On board analog-to-digital converters
- 10 Msample/sec voltage A/D
- 1 Msample/sec current A/D
Related Literature
• ISL6590 Datasheet
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB379 “Thermal Characterization of
Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Primarion is a registered trademark of Primarion, Inc. Primarion PowerCode is a trademark of Primarion, Inc
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
ISL6580
Typical Power Stage Schematic
2

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Typical Application
3.3 V
1.8 V
VDD_IO VDD_CORE
VID[0:5]
PWRGD
OUTEN
ARX
ATX
ERR
SOC
SCLK
SDATA
SYSCLK
PWM
IDIG
NDRIVE
ISL6590
ATRH
ATRL
OSC_IN
OSC_OUT
TEST1
TEST2
TEST3
TEST4
PWM
IDIG
NDRIVE
MDO
MDI
MCS
MCLK
PWM
IDIG
NDRIVE
GND
ISL6580
2.5 V
3.3 V 5-12 V 12 V
VDD VDRIVE VCC
VREF
ATRH
ATRL
VSENP
VSENN
ISL6580
ERR
SOC
ISENSE
SCLK
SDATA
VSW
CLK
NGATE
PWM
IDIG
NDRIVE
PGND
GND
REGULATION
CHANNEL
3.3 V 5-12 V 12 V
VDD VDRIVE VCC
VREF
ATRH
ATRL
VSENP
VSENN
ISL6580
ERR
SOC
SCLK
SDATA
CLK
ISENSE
VSW
NGATE
PWM
IDIG
NDRIVE
PGND
GND
ATR CHANNEL
3.3 V 5-12 V 12 V
VDD VDRIVE VCC
VREF
ATRH
ATRL
VSENP
VSENN
ISL6580
ERR
SOC
SCLK
SDATA
CLK
ISENSE
VSW
NGATE
PWM
IDIG
NDRIVE
PGND
GND
CONTROLLER
INTERFACE BUS
UV/OV
CHANNEL
3
VOUT
VOUT
RTN

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ISL6580
Functional Pin Description
PIN # NAME I/O
TYPE
DESCRIPTION
1 SDATA I/O 3.3V CMOS Digital I/O; serial data line that carries configuration and monitoring information to and from the Intersil
ISL6590 digital controller via the shared controller interface bus. Information transmitted via SDATA
includes: PVID information, input UVLO fault, output under/over voltage fault, thermal shutdown fault,
peak current limit setpoint, ATRH and ATRL trip levels
2
PWM
I 3.3V CMOS Digital input; pulse width modulation input to the high side driver.
3 NDRIVE I 3.3V CMOS Digital input; multifunction pin used for assigning device ID at startup. During operation, provides
pulse width modulation for the low side driver
4
GND
I
GND IC ground
5 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
6 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
7 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
8 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
9 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
10 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
11 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
12
GND
I
GND IC ground
13
GND
I
GND IC ground
14 VDRIVE I VDRIVE Power input typically connected to a 5V supply. Provides the supply voltage for driving the gate of the
Low side NFET
15 VDRIVE I VDRIVE Power input typically connected to a 5V supply. Provides the supply voltage for driving the gate of the
Low side NFET
16
GND
I
GND IC ground
17
GND
I
GND IC ground
18
GND
I
GND IC ground
19
GND
I
GND IC ground
20 NGATE O HV ANALOG High voltage analog output used to drive the low side NFET. When NDRIVE is high, NGATE is
switched to VDRIVE. When NDRIVE is low, NGATE is switched to ground.
21 NGATE O HV ANALOG High voltage analog output used to drive the low side NFET. When NDRIVE is high, NGATE is
switched to VDRIVE. When NDRIVE is low, NGATE is switched to ground.
22 NGATE O HV ANALOG High voltage analog output used to drive the low side NFET. When NDRIVE is high, NGATE is
switched to VDRIVE. When NDRIVE is low, NGATE is switched to ground.
23 NGATE O HV ANALOG High voltage analog output used to drive the low side NFET. When NDRIVE is high, NGATE is
switched to VDRIVE. When NDRIVE is low, NGATE is switched to ground.
24
GND
I
GND IC ground
25
GND
I
GND IC ground
26
GND
I
GND IC ground
27
GND
I
GND IC ground
28 VDRIVE I VDRIVE Power input typically connected to a 5V supply. Provides the supply voltage for driving the gate of the
low side NFET
29 VDRIVE I VDRIVE Power input typically connected to a 5V supply. Provides the supply voltage for driving the gate of the
low side NFET
30
GND
I
GND IC ground
31
GND
I
GND IC ground
32 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
4

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ISL6580
Functional Pin Description (Continued)
PIN # NAME I/O
TYPE
DESCRIPTION
33 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
34 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
35 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
36 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
37 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
38 VSW O HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW
39
GND
I
GND IC ground
40 ISENSE I
MINUS/
GND
GND Ground pin for current sense resistor
41 ISENSE I/O ANALOG Low voltage analog output; current representing 1/9900 of the high side PFET current
PLUS
42 SOC O 3.3V CMOS Digital outupt; start of conversion signal (SOC). This signal frames the error word generated by the
voltage A/D when configured in regulation mode.
43
GND
I
GND
IC ground
44 IDIG O 3.3V CMOS Digital output; 7 bit serial word transmitted typically at 66.67MHz. The first bit is a start bit (start=1).
This signal represents the sampled peak current in the high side PFET, MSB first
45
VDD
I
VDD
Power supply for the logic typically set at 3.3V
46 VREF I VREF Low voltage analog input; 2.5V reference signal used by the A/D converter and the thermal shutdown
circuits
47
GND
I
GND IC ground
48 CLK I 3.3V CMOS Digital input; typically a 133MHz clock supplied to the Intersil ISL6590
49 ERR O 3.3V CMOS Digital output; Voltage A/D output word indicating the error from the desired output voltage and
VSENP-VSENN measured voltage (Output voltage-VID). The error signal is a 6 bit serial word (MSB
first) transmitted typically at 66.67MHz.
50 ATRL O 3.3V CMOS Digital output; Active Transient Response Low (ATRL). ATRL indicates the regulated output voltage
has"spiked" above the programmed level.
51 ATRH O 3.3V CMOS Digital output; Active Transient Response High (ATRH). ATRH indicates the regulated output voltage
has"drooped" below the programmed level.
52
GND
I
GND IC ground
53 VSENN I LV ANALOG Low voltage analog input; negative input for the remote sense used to differentially sense the
regulated output voltage. The IC is configurable for thre modes of operation: Regulation mode, ATR
mode, and output OV/UV mode
54 VSENP I LV ANALOG Low voltage analog input; positive input for the remote sense used to differentially sense the regulated
output voltage. The IC is configurable for thre modes of operation: Regulation mode, ATR mode, and
output OV/UV mode
55
VDD
I
VDD
Power supply for the logic typically set at 3.3V
56 SCLK I 3.3V CMOS Digital input; typically 16.67MHz clock supplied by the Intersil ISL6590 digital controller for the
controller interface bus Paddle
PADDLE VCC
I
VCC
Power supply input typically set at 12V. Provides gate drive and source connection for the integrated
high side PFET
Side Bar
1
VSW
O HV ANALOG Drain of high side PFET. When the PWM signal is high, VCC is switched to VSW
Side Bar
2
VSW
O HV ANALOG Drain of high side PFET. When the PWM signal is high, VCC is switched to VSW
5