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®
Data Sheet
April 2003
ISL6590
FN9061
Digital Multi-Phase PWM Controller for
Core-Voltage Regulation
Processors that operate above a GHz require fast, intelligent
power systems. The Intersil ISL6590 controller offers
intelligent digital, multi-phase control that provides high
bandwidth, optimal control frequency response, noise
immunity and active transient response control algorithms.
The design is fully scalable for controlling up to six phases,
each featuring the Intersil ISL6580 intelligent power stage.
The user can configure and monitor the power system via
the Asynchronous Serial Interface (ASI). The ISL6590
controller flexibility can be extended with the addition of an
external EEPROM for updating key circuit operating
parameters in the control loop and overall system design.
The digital architecture reduces the design time for
engineers with the use of our software. The software allows
the designer the freedom to choose output stage
components and still achieve optimized system
performance.
The ISL6590 digital controller communicates with the
ISL6580 integrated power stages via 100% digital signaling.
Serial communication allows for separation of the controller
and the power stage, providing placement and layout
freedom to the power stage. The digital controller
implements phase balancing to ensure even distribution of
phase currents. The ISL6590 controller configures the
ISL6580 power stage current limit, VID reference, non-
overlap period, Active Transient Response (ATR) trigger
levels and maximum temperature limit. The digital controller
also monitors the ISL6580 power stage peak currents, over-
temperature fault, input under voltage, output over/under
voltage to ensure proper operation of the power supply.
Pinout
ISL6590 (QFN)
TOP VIEW
OUTEN
VID [0]
VID [1]
VID [2]
VID [3]
VID [4]
VID [5]
VDD_CORE
PWRGD
VDD_IO
MCLK
MDO
MDI
MCS
NDRIVE1
PWM1
64
01
16
17
49
48
TEST 2
ATRL
SOC
ERR
VDD_IO
SYS_CLK
VDD_IO
NC
NC
VDD_CORE
NC
NC
IDIG6
PWM6
NDRIVE6
33
32
TEST1
Features
• Open Architecture features software programmable
control loop compensation enabling optimal system
performance
- User accessible asynchronous serial interface
• Intel VR10
- 6-bit Dynamic VID™
- Output voltage regulation range of 0.8375V to 1.600Vdc
• 250kHz to 1MHz switching frequency
• 100% digital control and signaling
• Active Transient Response (ATR) control algorithms for
minimized voltage droop and overshoot
• Controls up to six ISL6580 intelligent power stages (20A
per phase, 120A total system current)
• Programmable Adaptive voltage positioning (AVP) load
line
• Configurable control loop parameters (with optional
external EEPROM)
• Programmable MOSFET dead time control
• High speed voltage and current control loops
• PWRGD and OUTEN
• Serial interface to ISL6580 power stages for system
monitoring and configuration
• 64 Ld 9x9 QFN package
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
ISL6590DR
0 to 85 64 Ld 9x9 QFN L64.9x9-S
1 CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc.

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ISL6590
Typical Application Circuit
3.3 V
1.8 V
VDD_IO VDD_CORE
V ID[0:5]
PW RG D
OUTEN
A RX
ATX
ERR
SOC
SCLK
SDA TA
SY SCLK
PW M
IDIG
NDRIV E
ISL6590
A TRH
A TRL
OSC_IN
OSC_OUT
TEST1
TEST2
TEST3
TEST4
PW M
IDIG
NDRIV E
MDO
MDI
MCS
MCLK
PW M
IDIG
NDRIV E
GND
2.5 V
3.3 V 5-12 V 12 V
VDD VDRIVEVCC
V REF
A TRH
A TRL
V SENP
V SENN
ISL6580
ERR
SOC
IS ENS E
SCLK
SDA TA
V SW
CLK
NGA TE
PW M
IDIG
NDRIV E
PGND
GND
R EGU L ATI ON
C H AN N EL
3.3 V 5-12 V 12 V
VDD VDRIVEVCC
V REF
A TRH
A TRL
V SENP
V SENN
ISL6580
ERR
SOC
SCLK
SDA TA
CLK
IS ENS E
V SW
NGA TE
PW M
IDIG
NDRIV E
PGND
GND
ATR CHANNEL
3.3 V 5-12 V 12 V
VDD VDRIVEVCC
V REF
A TRH
A TRL
V SENP
V SENN
ISL6580
ERR
SOC
SCLK
SDA TA
CLK
IS ENS E
V SW
NGA TE
PW M
IDIG
NDRIV E
PGND
GND
UV/OV CHANNEL
CONTROLLER
INTERFACE BUS
2
Vout
Vout
RTN

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ISL6590
Absolute Maximum Ratings
Supply Voltage
(VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63V
(VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.98V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Recommended Operating Conditions
Supply Voltage
(VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±5%
(VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%
(Analog PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%
(Digital PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
Thermal Information
Thermal Resistance
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . .
θJA-0 LFPM AIR. . . . . . . . . . . . . . . . . . .
θJA-100 LFPM AIR . . . . . . . . . . . . . . . . .
θJA-200 LFPM AIR . . . . . . . . . . . . . . . . .
θJA-400 LFPM AIR . . . . . . . . . . . . . . . . .
θJB . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(oC/W)
3
29.0
26.6
25.0
23.2
8
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a “High Effective” Thermal Conductivity Board with “Direct Attach” features. (See Tech Brief
TB379 for details.)
Electrical Specifications Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX
INPUTS
Outen, VID[0:5], VIH
Outen, VID[0:-5], VIL
MDI, IDIG[1-6], ATRL, ATRH, SOC,
ERR VIH
MDI, IDIG[1-6], ATRL, ATRH, SOC,
ERR VIL
EXT_RESETB, VIH
EXT_RESETB, VIL
ARX, VIH
ARX, VIL
OSC_IN, VIH
OSC_IN, VIL
OUTPUTS
3.3V no internal pull-up/down resistors
3.3V no internal pull-up/down resistors
3.3V internal pull-down resistor
3.3V internal pull-down resistor
3.3V internal pull-up resistor
3.3V internal pull-up resistor
3.3V internal pull-up resistor
3.3V internal pull-up resistor
No internal pull-up/down resistors
No internal pull-up/down resistors
0.8 -
-
- - 0.4
2.0 -
-
- - 0.8
2.0 -
-
- - 0.8
2.0 -
-
- - 0.8
2.0 -
-
- - 0.8
MCLK, MDO, MCS, NDRIVE[0:5],
PWM[0:5], ATX, VOH
MCLK, MDO, MCS, NDRIVE[0:5],
PWM[0:5], ATX, VOL
SYS_CLK, VOH
SYS_CLK, VOL
SCLK, VOH
SCLK, VOL
SDATA, VOH
SDATA, VOL
SDATA, VIH
SDATA, VIL
PWRGD, VOH
PWRGD, VOL
OSC_OUT, VOH
OSC_OUT, VOL
No internal pull-up/down resistors, 8mA drive
No internal pull-up/down resistors, 8mA drive
No internal pull-up/down resistors, 20mA drive
No internal pull-up/down resistors, 20mA drive
No internal pull-up/down resistors, 16mA drive
No internal pull-up/down resistors, 16mA drive
3.3V pull-up resistor, 16mA drive
3.3V pull-up resistor, 16mA drive
3.3V pull-up resistor
3.3V pull-up resistor
Open drain, 6mA drive
Open drain, 6mA drive
No internal pull-up/down resistors, 10mA drive
No internal pull-up/down resistors, 10mA drive
2.4 -
-
- - 0.4
2.4 -
-
- - 0.4
2.4 -
-
- - 0.4
2.4 -
-
- - 0.4
2.0 -
-
- - 0.8
2.4 -
-
- - 0.4
2.4 -
-
- - 0.4
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3

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ISL6590
Electrical Specifications Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
POWER-ON RESET AND ENABLE
POR Threshold
OUTEN Threshold
Vddio Rising
Vddio Falling
Vddcore Rising
Vddcore Falling
OUTEN Rising
1.4 -
-
- - 2.55
0.7 -
-
- - 1.4
- 0.71 -
V
V
V
V
V
OUTEN Falling
- 0.64 -
V
OSCILLATOR
Adjustment Range
0.250
-
1 MHz
Max Duty Cycle
24 TBD
-
%
NOTE:
1. Reserved for note.
Block Diagram
Ext_Reset
ATX
ARX
OUTEN
PWRGD
VID[5:0]
MDI
MCLK
MCS
MDO
OSC_OUT
OSC_IN
PLL_FILTER
POR
Asynchronous
Serial Interface
State
Control and
Fault
Monitor
Memory Bus
MUX
Feedback
Control PWM Driver
Current
Loop
Voltage
Loop
Clock
Distribution
Non-Volatile
SPI EEPOM
Interface
State
Machine
Control/
Status
Registers
MHz Memory
Mapped
Registers
AVP
Backside Serial
Bus
FIGURE 1. ISL6590 BLOCK DIAGRAM
PWM [6:1]
NDRIVE [6:1]
ATRH
ATRL
IDIG[6:1]
SOC
ERR
SCLK
SDATA
SYS_CLK
4

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ISL6590
Pin Descriptions
PIN NO.
1
PIN NAME
OUTEN
2-7
8, 21, 39, 57
9
VID[0:5]
VDD_CORE
PWRGD
10, 25, 42,
44, 54
11
VDD_IO
MCLK
12
13
14
15, 18, 22,
26, 30, 34
16, 19, 23,
27, 31, 35
17, 20, 24,
28, 32, 36
MDO
MDI
MCS
NDRIVE[1:6]
PWM[1:6]
IDIG[1:6]
29
33, 48, 50,
51
37, 38, 40,
41
43
EXT_Reset
TEST[1:4]
NC
SYSCLK
45 ERR
46 SOC
47 ATRL
49 ATRH
52 SDATA
53 SCLK
55 ATX
56 ARX
58 OSC_OUT
59 OSC_IN
60 PLL_DIG_VSS
PLL Bypass
61 PLL_DIG_VDD
62 PLL_ANA_VSS
63 PLL_ANA_VDD
64 PLL_Filter
65 GND
TYPE
Input
Input
Power
Output
Power
PIN DESCRIPTION
Output enable high input signal used to command the regulator on and a low input signal turns
the regulator off.
Voltage identification (6 bit). Programs Vout regulation voltage.
IC internal core supply voltage (1.8 VDC logic).
Power Good high output signal to indicate the regulator output voltage is within the specified
range. A low signal indicates the voltage is not within range.
IC I/O input supply voltage (3.3 VDC logic).
Output
Output
Input
Output
Output
EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is
clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs.
EEPROM external memory data output. Compliant with SPI EEPROMs.
EEPROM external memory data input. Compliant with SPI EEPROMs.
EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs.
Low side drive signal used to initiate the ISL6580 to turn on the LSFET.
Output PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices.
Input
Input
Output
Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The
remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580
P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.)
IDIG is an input that is received at SYSCLK/2, normally 66.6MHz.
Voltage identification (6 bit). Programs Vout regulation voltage.
Test pins for part evaluation
N/A These pins have not been bonded out.
Input/Output System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the
internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency.
Input
Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into
the control loop and used to regulate the output voltage.
Input
Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal.
Input
Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on
the converter output.
Input
Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the
converter output.
Input/Output Controller serial interface for communication, monitoring, and configuration data between the
ISL6580 and ISL6590 controller.
Output
Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the
Backside serial bus.
Output Asynchronous Serial Interface Transmit
Input
Asynchronous Serial Interface Receive
Output Only used if part is using a crystal to generate the system clock.
Input
Ground
Input
Requires a 33.33MHz oscillator or crystal which is used to generate system clock.
Digital Ground for the 4X clock multiplier PLL.
Test mode to bypass PLL input to core.
Power 1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic).
Ground Analog Ground for the 4X clock multiplier PLL.
Power 1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic).
Analog Input Filter cap for PLL.
Ground Paddle IC Ground
5