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May 9, 2006
ISL6605
FN9091.7
Synchronous Rectified MOSFET Driver
The ISL6605 is a high frequency, MOSFET driver optimized
to drive two N-Channel power MOSFETs in a synchronous-
rectified buck converter topology. This driver combined with
an Intersil HIP63xx or ISL65xx Multi-Phase Buck PWM
controller forms a complete single-stage core-voltage
regulator solution with high efficiency performance at high
switching frequency for advanced microprocessors.
The IC is biased by a single low voltage supply (5V) and
minimizes low driver switching losses for high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3000pF load with an 8ns
propagation delay and less than 10ns transition time. This
product implements bootstrapping on the upper gate with an
internal bootstrap Schottky diode, reducing implementation
cost, complexity, and allowing the use of higher
performance, cost effective N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
The ISL6605 features 4A typical sink current for the lower
gate driver, which is capable of holding the lower MOSFET
gate during the Phase node rising edge to prevent shoot-
through power loss caused by the high dv/dt of the Phase
node.
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall Time
- Ultra Low Propagation Delay 8ns
• Three-State PWM Input for Power Stage Shutdown
• Internal Bootstrap Schottky Diode
• Low Bias Supply Current (5V, 30µA)
• Enable Input
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
The ISL6605 also features a Three-State PWM input that,
working together with Intersil multi-phase PWM controllers,
will prevent a negative transient on the output voltage when
the output is being shut down. This feature eliminates the
Schottky diode that is usually seen in a microprocessor
power system for protecting the microprocessor from
reversed-output-voltage damage.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinouts
ISL6605
(8 LD SOIC)
TOP VIEW
ISL6605
(8 LD QFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 EN
6 VCC
5 LGATE
BOOT 1
PWM 2
87
34
66 EN
5 VCC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2006. All Rights Reserved
Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.
All other trademarks mentioned are the property of their respective owners.

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ISL6605
Ordering Information
PART
NUMBER*
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
ISL6605CB ISL6605CB
0 to 70 8 Ld SOIC M8.15
ISL6605CBZ ISL6605CBZ
(Note)
0 to 70 8 Ld SOIC
(Pb-free)
M8.15
ISL6605CBZA ISL6605CBZ
(Note)
0 to 70 8 Ld SOIC
(Pb-free)
M8.15
ISL6605CR 605C
0 to 70 8 Ld 3x3 QFN L8.3x3
ISL6605CRZ 05CZ
(Note)
0 to 70 8 Ld 3x3 QFN L8.3x3
(Pb-free)
ISL6605CRZA 05CZ
(Note)
0 to 70 8 Ld 3x3 QFN L8.3x3
(Pb-free)
ISL6605IB
ISL6605IB
-40 to 85 8 Ld SOIC M8.15
ISL6605IBZ
(Note)
6605IBZ
-40 to 85 8 Ld SOIC
(Pb-free)
M8.15
Ordering Information
PART
NUMBER*
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
ISL6605IBZA 6605IBZ
(Note)
-40 to 85 8 Ld SOIC
(Pb-free)
M8.15
ISL6605IR
605I
-40 to 85 8 Ld 3x3 QFN L8.3x3
ISL6605IRZ
(Note)
05IZ
-40 to 85 8 Ld 3x3 QFN L8.3x3
(Pb-free)
ISL6605IRZA 05IZ
(Note)
-40 to 85 8 Ld 3x3 QFN L8.3x3
(Pb-free)
ISL6558EVAL2 Evaluation Platform (ISL6558IR+ISL6605IR)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ti
Block Diagram
ISL6605
VCC
EN
VCC
PWM
20K
20K
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
VCC
BOOT
UGATE
PHASE
LGATE
GND
2 FN9091.7
May 9, 2006

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ISL6605
Typical Application - Multi-Phase Converter Using ISL6605 Gate Drivers
+5V
PGOOD
VID
(OPTIONAL)
+5V
FB COMP
VCC
VSEN
PWM1
PWM2
PWM
CONTROL
(HIP63XX
or ISL65XX)
ISEN1
ISEN2
FS/EN
GND
+5V
VCC
EN
BOOT
UGATE
PWM
ISL6605
499K*
PHASE
LGATE
+5V
VCC
BOOT
EN
PWM
499K* ISL6605
UGATE
PHASE
LGATE
VIN
VIN
+VCORE
* 499K IS USED TO PULL DOWN THE PWM INPUT TO PREVENT THE PWM FROM FALSE TRIGGERING UGATE DURING STARTUP.
3 FN9091.7
May 9, 2006

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ISL6605
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT). . . . . . . -0.3V to 22V (DC) or 33V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . . . . . -0.3V to 7V
PHASE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to 28V (<200ns)
. . . . . . . . . . GND - 5V (<100ns Pulse Width, 10μJ) to 28V (<200ns)
UGATE Voltage . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT+0.3V
. . . . . . . VPHASE - 4V (<200ns Pulse Width, 20μJ) to VBOOT+0.3V
LGATE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to VVCC + 0.3V
. . . . . . . . . . . GND - 2V (<100ns Pulse Width, 4μJ) to VVCC + 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C
ESD Rating
HBM Class 1 JEDEC STD
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Thermal Resistance (Notes 1, 2, & 3) θJA(°C/W) θJC(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 110
N/A
QFN Package (Notes 2, 3). . . . . . . . . . 95
36
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3. θJC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications These specifications apply for TA = -40°C to 85°C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
VCC SUPPLY CURRENT
Bias Supply Current
Bias Supply Current
PWM INPUT
IVCC
IVCC
EN = LOW, TA = 0°C to 70°C
EN = LOW, TA = -40°C to 85°C
PWM pin floating, VVCC = 5V
-
-
-
Input Current
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Holdoff Time
EN INPUT
IPWM
VPWM = 5V
VPWM = 0V
VVCC = 5V, TA = 0°C to 70°C
VVCC = 5V, TA = -40°C to 85°C
VVCC = 5V
VVCC = 5V, temperature = 25°C
-
-
-
-
3.3
-
EN LOW Threshold
1.0
EN HIGH Threshold
-
SWITCHING TIME
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
OUTPUT
tRUGATE
tRLGATE
tFUGATE
tFLGATE
tPDLUGATE
tPDLLGATE
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
-
-
-
-
-
-
Upper Drive Source Resistance
Upper Driver Source Current (Note 4)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 4)
Lower Drive Source Resistance
Lower Driver Source Current (Note 4)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 4)
NOTE:
RUGATE
IUGATE
RUGATE
IUGATE
RLGATE
ILGATE
RLGATE
ILGATE
500mA Source Current
VUGATE-PHASE = 2.5V
500mA Sink Current
VUGATE-PHASE = 2.5V
500mA Source Current
VLGATE = 2.5V
500mA Sink Current
VLGATE = 2.5V
-
-
-
-
-
-
-
-
4. Guaranteed by design. Not 100% tested in production.
TYP
-
-
30
250
-250
-
-
-
420
-
-
8
8
8
4
8
8
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
MAX UNITS
1.5 μA
2 μA
- μA
- μA
- μA
1.70 V
1.75 V
-V
- ns
-V
2.0 V
- ns
- ns
- ns
- ns
- ns
- ns
2.5 Ω
-A
2.5 Ω
-A
2.5 Ω
-A
1.0 Ω
-A
4 FN9091.7
May 9, 2006

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ISL6605
Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
PINOUT diagrams for QFN pin numbers.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see the
three-state PWM Input section under DESCRIPTION for further
details). Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
EN (Pin 7)
Enable input pin. Connect this pin to HIGH to enable and
LOW to disable the IC. When disabled, the IC draws less
than 1μA bias current.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. This pin provides a return path
for the upper gate driver.
Timing Diagram
Thermal Pad (in QFN only)
In the QFN package, the pad underneath the center of the
IC is a thermal substrate. The PCB “thermal land” design
for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
Description
Operation
Designed for speed, the ISL6605 MOSFET driver controls both
high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [tPDLLGATE], the lower gate begins to fall. Typical fall
times [tFLGATE] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[tPDHUGATE] based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-
through. Once this delay period is completed the upper gate
drive begins to rise [tRUGATE] and the upper MOSFET turns
on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLUGATE] is encountered before the
upper gate begins to fall [tFUGATE]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
tPDHLGATE. The upper MOSFET gate voltage is monitored
and the lower gate is allowed to rise after the upper MOSFET
gate-to-source voltage drops below 1V. The lower gate then
rises [tRLGATE], turning on the lower MOSFET.
PWM
tPDHUGATE
UGATE
LGATE
tPDLLGATE
tFLGATE
tRUGATE
tPDLUGATE
tFUGATE
tPDHLGATE
tRLGATE
5 FN9091.7
May 9, 2006