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®
Data Sheet
June 2004
ISL6614A
FN9160
Dual Advanced Synchronous Rectified
Buck MOSFET Drivers with Pre-POR OVP
The ISL6614A integrates two ISL6613A MOSFET drivers and
is specifically designed to drive two Channel MOSFETs in a
synchronous rectified buck converter topology. These drivers
combined with HIP63xx or ISL65xx Multi-Phase Buck PWM
controllers and N-Channel MOSFETs form complete core-
voltage regulator solutions for advanced microprocessors.
The ISL6614A drives both the upper and lower gates
simultaneously over a range from 5V to 12V. This drive-
voltage provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during startup.
The ISL6614A also features a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6614ACB
0 to 85 14 Ld SOIC
M14.15
ISL6614ACB-T 14 Ld SOIC Tape and Reel
ISL6614ACR
0 to 85 16 Ld 4x4 QFN
L16.4x4
ISL6614ACR-T 16 Ld 4x4 QFN Tape and Reel
ISL6614ACBZ *
0 to 85 14 Ld SOIC (Pb-Free) M14.15
ISL6614ACBZ-T * 14 Ld SOIC Tape and Reel (Pb-Free)
ISL6614ACRZ *
0 to 85 16 Ld 4x4 QFN (Pb-Free) L16.4x4
ISL6614ACRZ-T * 16 Ld 4x4 QFN Tape and Reel (Pb-Free)
* Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
Contact the factory for availability.
Features
• Pin-to-pin Compatible with HIP6602 SOIC family
• Quad N-Channel MOSFET Drives for Two Synchronous
Rectified Bridges
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Available
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC-DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief 400 and 417 for Power Train Design,
Layout Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6614ACB/ISL6614ACBZ (SOIC)
TOP VIEW
PWM1 1
PWM2 2
GND 3
LGATE1 4
PVCC 5
PGND 6
LGATE2 7
14 VCC
13 PHASE1
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
8 PHASE2
ISL6614A
ISL6614ACR/ISL6614ACRZ (16 LEAD QFN)
TOP VIEW
16 15 14 13
GND 1
LGATE1 2
PVCC 3
PGND 4
GND
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
5678
Block Diagram
VCC
+5V
PVCC
OTP &
PRE-POR OVP
FEATURES
10K
PWM1
8K
SHOOT-
THROUGH
PROTECTION
PVCC
CONTROL
+5V LOGIC
10K
PWM2
GND
8K
PGND
PVCC
SHOOT-
THROUGH
PROTECTION
BOOT1
UGATE1
PHASE1
CHANNEL 1
LGATE1
PGND
BOOT2
UGATE2
PHASE2
PVCC
CHANNEL 2
LGATE2
PGND
PAD FOR ISL6614ACR, THE PAD ON THE BOTTOM SIDE OF
THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2

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ISL6614A
Typical Application - 4 Channel Converter Using ISL65xx and ISL6614A Gate Drivers
+12V
VCC
BOOT1
UGATE1
PHASE1
+12V
PGOOD
EN
VID
+5V
FB COMP
VSEN
VCC
ISEN1
PWM1
PWM2
MAIN ISEN2
CONTROL
ISL65xx
LGATE1
DUAL
DRIVER
ISL6614A
PVCC
5V TO 12V
BOOT2
+12V
PWM1
PWM2
UGATE2
PHASE2
LGATE2
GND
PGND
FS/DIS
ISEN3
PWM3
PWM4
GND ISEN4
+12V
VCC
BOOT1
UGATE1
PHASE1
+12V
LGATE1
DUAL
DRIVER
ISL6614A
PVCC
5V TO 12V
BOOT2
+12V
PWM1
PWM2
UGATE2
PHASE2
LGATE2
GND
PGND
+VCORE
3

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ISL6614A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC (VPVCC = 12V)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance (Typ. Notes 1, 2, 3). . θJA (°C/W) θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
90
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
46
9
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
IVCC
IPVCC
fPWM = 300kHz, VPVCC = 12V
fPWM = 300kHz, VPVCC = 12V
- 7.1 - mA
- 9.7 - mA
VCC Rising Threshold
9.35 9.80 10.00
V
VCC Falling Threshold
7.35 7.60 8.00
V
PWM INPUT (See Timing Diagram on Page 6)
Input Current
PWM Rising Threshold
IPWM
VPWM = 5V
VPWM = 0V
VCC = 12V
- 450 -
- -400 -
- 3.00 -
µA
µA
V
PWM Falling Threshold
VCC = 12V
- 2.00 -
V
Typical Three-State Shutdown Window
VCC = 12V
1.80 - 2.40 V
Three-State Lower Gate Falling Threshold
VCC = 12V
- 1.50 -
V
Three-State Lower Gate Rising Threshold
VCC = 12V
- 1.00 -
V
Three-State Upper Gate Rising Threshold
VCC = 12V
- 3.20 -
V
Three-State Upper Gate Falling Threshold
VCC = 12V
- 2.60 -
V
Shutdown Holdoff Time
UGATE Rise Time
LGATE Rise Time
tTSSHD
- 245 -
tRU VPVCC = 12V, 3nF Load, 10% to 90%
-
26
-
tRL VPVCC = 12V, 3nF Load, 10% to 90% - 18 -
ns
ns
ns
4

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ISL6614A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
tFU
tFL
tPDHU
tPDHL
tPDLU
tPDLL
tPDTS
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
-
-
-
-
-
-
-
Upper Drive Source Current (Note 4)
IU_SOURCE VPVCC = 12V, 3nF Load
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
Upper Drive Sink Current (Note 4)
IU_SINK VPVCC = 12V, 3nF Load
Upper Drive Transition Sink Impedance (Note 3) RU_SINK_TR
Upper Drive DC Sink Impedance
RU_SINK_DC 150mA Source Current
Lower Drive Source Current (Note 4)
IL_SOURCE VPVCC = 12V, 3nF Load
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
Lower Drive Sink Current (Note 4)
IL_SINK VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
NOTE:
4. Guaranteed by design. Not 100% tested in production.
-
1.25
-
-
0.9
-
0.85
-
0.60
TYP
18
12
10
10
10
10
10
1.25
2.0
2
1.3
1.65
2
1.25
3
0.80
MAX
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
-A
3.0
-A
2.2
3.0
-A
2.2
-A
1.35
5