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®
Data Sheet
December 29, 2004
ISL6700
FN9077.6
80V/1.25A Peak, Medium Frequency, Low
Cost, Half-Bridge Driver
The ISL6700 is an 80V/1.25A peak, medium frequency, low
cost, half-bridge driver IC available in 8-lead SOIC and
12-lead QFN plastic packages. The low-side and high-side
gate drivers are independently controlled and matched to
25ns. This gives the user maximum flexibility in dead-time
selection and driver protocol. Undervoltage protection on
both the low-side and high-side supplies force the outputs
low. Non-latching, level-shift translation is used to control the
upper drive circuit. Unlike some competitors, the high-side
output returns to its correct state after a momentary
undervoltage of the high-side supply.
Ordering Information
PART
TEMP. RANGE
NUMBER
(°C)
PACKAGE PKG. DWG. #
ISL6700IB
-40 to 125 8 Ld SOIC
M8.15
ISL6700IBZ
(See Note)
-40 to 125
8 Ld SOIC
(Pb-free)
M8.15
ISL6700IR
-40 to 125 12 Ld 4x4 QFN L12.4x4
ISL6700IRZ
(See Note)
-40 to 125
12 Ld 4x4 QFN L12.4x4
(Pb-free)
Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6700IB (SOIC)
TOP VIEW
VDD 1
HI 2
LI 3
VSS 4
8 HB
7 HO
6 HS
5 LO
Features
• Drives 2 N-Channel MOSFETs in Half-Bridge
Configuration
• Space Saving SO8 and Low RC-S QFN Packages
• Phase Supply Max Voltage to 80VDC
• Bootstrap Supply Max Voltage to 96VDC
• Drives 1000pF Load with Rise and Fall Times Typ. 15ns
• TTL/CMOS Compatible Input Thresholds
• Independent Inputs for Non-Half-Bridge Topologies
• No Start-Up Problems
• Low Power Consumption
• Wide Supply Range
• Supply Undervoltage Protection
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN
- Quad Flat No Leads - Package Outline
• Pb-Free Available (RoHS Compliant)
Applications
• Telecom/Datacom Power Supplies
• Half-Bridge Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
ISL6700IR (QFN)
TOP VIEW
12 11 10
HI 1
9 HO
NC 2
EPAD
8 NC
LI 3
7 HS
456
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

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ISL6700
Application Block Diagram
+12V
+48V
VDD
HB
SECONDARY
CIRCUIT
HI
PWM
CONTROLLER
LI
DRIVE
HI
DRIVE
LO
HO
HS
LO
ISL6700
VSS
REFERENCE
AND
ISOLATION
Functional Block Diagram
HI
U/V
LEVEL
SHIFT
LI
VDD
VSS
DETECTOR
UNDERVOLTAGE
TURN-ON
DELAY
EPAD (QFN PACKAGE ONLY)
HB
HO
HS
LO
2 FN9077.6
December 29, 2004

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+12V
PWM
ISL6700
+48V
ISL6700
SECONDARY
CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+12V
PWM
+48V
ISL6700
SECONDARY
CIRCUIT
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
3 FN9077.6
December 29, 2004

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ISL6700
Absolute Maximum Ratings
Supply Voltage, VDD (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V
LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Voltage on HB (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHS+VDD
Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . VSS-0.3 to VDD+0.3V
Voltage on HO (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHB+0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V
Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . VHS +7.5V to VHS +VDD
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
SOIC (Note 3) . . . . . . . . . . . . . . . . . . .
95
N/A
QFN (Note 4) . . . . . . . . . . . . . . . . . . . .
49
7
Max Power Dissipation at 25°C in Free Air (SOIC, Note 3). 1.316W
Max Power Dissipation at 25°C in Free Air (QFN, Note 4) . .2.976W
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . .-40°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
1. All voltages referenced to VSS unless otherwise specified.
2. Based on VDD=15V. The magnitude of the allowable negative transient on the HS pin is a function of the VDD supply voltage. VHS<15.6V-
VDD+VF, where VHS is the magnitude of the allowable negative transient and VF is the forward voltage drop of the bootstrap diode.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
PARAMETERS
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = 25°C
TJ = -40°C TO
125°C
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN MAX UNITS
SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION
VDD Quiescent Current
VDD Operating Current
VDD Operating Current
HB Off Quiescent Current
HB On Quiescent Current
HB Operating Current
HB Operating Current
HS Leakage Current
VDD Rising Undervoltage Threshold
VDD Falling Undervoltage Threshold
Undervoltage Hysteresis
IDD
IDDO
IDDO
IHBL
IHBH
IHBO
IHBO
IHLK
VDDUV+
VDDUV-
UVHYS
LI = 0 or VDD
f = 50kHz
f = 500kHz
HI = 0
HI = VDD
f = 50kHz, CL = 1000pF
f = 500kHz, CL = 1000pF
VHS = 80V
VHB = 96V
- 1.9 2.2 - 2.4 mA
- 2.0 2.2 - 2.5 mA
- 2.5 3.0 - 4.0 mA
- 1.25 1.5 - 1.8 mA
- 170 240 - 250 µA
- 1.45 1.8 - 2.0 mA
- 2.4 2.8 - 3.0 mA
- - 1 - 1 µA
6.8 7.6 8.25 6.5 8.5
6.5 7.1 7.8 6.25 8.1
0.17 0.45 0.75 0.15 0.90
V
V
V
HB Undervoltage Threshold
VHBUV Referenced to HS
4.8 5.3 6.5 4.0 7.5
V
INPUT PINS: LI and HI
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
VIL Full Operating Conditions
VIH Full Operating Conditions
0.8 1.6 - 0.8 -
V
- 1.7 2.2 - 2.2 V
- 100 - - - mV
Low Level Input Current
High Level Input Current
IIL VIN = 0V, Full Operating Conditions
IIH VIN = 5V, Full Operating Conditions
-70 -60 -30 -80 -30
30 115 130 30 145
µA
µA
4 FN9077.6
December 29, 2004

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ISL6700
Electrical Specifications
PARAMETERS
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = 25°C
TJ = -40°C TO
125°C
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN MAX UNITS
GATE DRIVER OUTPUT PINS: LO & HO
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
VOL
VDD-VOH
IO+
IO-
IOUT = 0A
IOUT = 0A
VOUT = 0V
VOUT = 12V
- - 0.1 - 0.1 V
- - 0.1 - 0.1 V
- 1.4 - - - A
- 1.3 - - - A
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = 25°C
MIN TYP MAX
TJ = -40°C
TO 125°C
MIN MAX UNITS
Lower Turn-off Propagation Delay
(LI Falling to LO Falling)
tLPHL
- 45 50 - 65 ns
Upper Turn-off Propagation Delay
(HI Falling to HO Falling)
tHPHL
- 60 75 - 90 ns
Lower Turn-on Propagation Delay
(LI Rising to LO Rising)
tLPLH
- 75 82 - 95 ns
Upper Turn-on Propagation Delay
(HI Rising to HO Rising)
tHPLH
- 70 75 - 95 ns
Deadtime, (tHPLH - tLPHL)
DHtON LI, HI switched simultaneously 0 24 - 0 - ns
Deadtime, (tLPLH - tHPHL)
DLtON
0 17 - 0 - ns
Rise Time
tR - 5 20 - 25 ns
Fall Time
tF - 5 20 - 25 ns
Delay Matching: Lower Turn-On and Upper Turn-Off
tMON
- 8 20 - 25 ns
Delay Matching: Lower Turn-Off and Upper Turn-On
tMOFF
- -15 25 - 30 ns
Pin Descriptions
SYMBOL
VDD
HI
LI
VSS
LO
HS
HO
HB
EPAD
DESCRIPTION
Positive supply to control logic and lower gate drivers. De-couple this pin to VSS. Connect anode of bootstrap diode to this pin.
Logic level input that controls the HO output.
Logic level input that controls the LO output.
Chip negative supply, generally will be ground.
Low-side output. Connect to gate of low-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
High-side output. Connect to gate of high-side power MOSFET.
High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive
side of bootstrap capacitor to this pin.
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
5 FN9077.6
December 29, 2004