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ISP1581
Universal Serial Bus 2.0 high-speed interface device
Rev. 02 — 23 October 2000
Objective specification
1. General description
The ISP1581 is a cost-optimized and feature-optimized Universal Serial Bus (USB)
interface device, which fully complies with the Universal Serial Bus Specification
Rev. 2.0. It provides high-speed USB communication capacity to systems based on a
microcontroller or microprocessor. The ISP1581 communicates with the system’s
microcontroller/processor through a high-speed general-purpose parallel interface.
The ISP1581 supports automatic detection of USB 2.0 system operation. The
USB 1.1 fall-back mode allows the device to remain operational under full-speed
conditions. It is designed as a generic USB interface device so that it can fit into all
existing device classes, such as: Imaging Class, Mass Storage Devices,
Communication Devices, Printing Devices and Human Interface Devices.
The internal generic DMA block allows easy integration into data streaming
applications. In addition, the various configurations of the DMA block are tailored for
mass storage applications.
The modular approach to implementing a USB interface device allows the designer to
select the optimum system microcontroller from the wide variety available. The ability
to re-use existing architecture and firmware investments shortens the development
c time, eliminates risk and reduces costs. The result is fast and efficient development of
c
the most cost-effective USB peripheral solution.
The ISP1581 is ideally suited for many types of peripherals, such as: printers;
scanners; magneto-optical (MO), compact disc (CD), digital video disc (DVD) and
Zip®/Jaz® drives; digital still cameras; USB-to-Ethernet links; cable and DSL
modems. The low power consumption during ‘suspend’ mode allows easy design of
equipment that is compliant to the ACPI™, OnNow™ and USB power management
requirements.
The ISP1581 also incorporates features such as SoftConnect™, a reduced
frequency crystal oscillator and integrated termination resistors. These features allow
significant cost savings in system design and easy implementation of advanced USB
functionality into PC peripherals.

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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
2. Features
s Complies fully with Universal Serial Bus Specification Rev. 2.0
s Complies with most Device Class specifications
s High performance USB interface device with integrated Serial Interface Engine
(SIE), FIFO memory, data transceiver and 3.3 V voltage regulators
s Supports automatic USB 2.0 mode detection and USB 1.1 fall-back mode
s High speed DMA interface
s Fully autonomous and multi-configuration DMA operation
s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints
s Integrated physical 8 kbyte of multi-configuration FIFO memory
s Endpoints with double buffering to increase throughput and ease real-time data
transfer
s Bus independent interface with most microcontroller/microprocessors
(16 Mbytes/s or 16 Mwords/s)
s Bus-powered capability with low power consumption and low ‘suspend’ current
s 12 MHz crystal oscillator with integrated PLL for low EMI
s Software controlled connection to the USB bus (SoftConnect™)
s Complies with the ACPI™, OnNow™ and USB power management requirements
s Internal power-on and low-voltage reset circuit, also supporting a software reset
s Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V
tolerant I/O pads
s Operating temperature range 40 to +85 °C
s 12 kV in-circuit ESD protection on human accessible pins such as D+ and D
s Full-scan design with high fault coverage (>99%)
s Available in LQFP64 package.
3. Applications
s Personal digital assistant (PDA)
s Mass storage device, e.g., Zip®, Jaz®, MO, CD, DVD drive
s Digital camera
s Communication device, e.g. router, modem
s Printer
s Scanner.
4. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
ISP1581BD
LQFP64 Plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
Version
SOT314-2
9397 750 07648
Objective specification
Rev. 02 — 23 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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3.3 V
1.5
k
RPU 7
RREF 8
12.2 k
(± 0.1%)
to/from USB
D+ D
65
SoftConnect
USB 2.0
TRANSCEIVER
12 MHz
XTAL1
60
XTAL2
59
40× PLL
OSCILLATOR
BIT CLOCK
RECOVERY
PHILIPS
SIE
MEMORY
MANAGEMENT
UNIT
RESET
10
POWER-ON
RESET
internal
reset
INTEGRATED
RAM
(8 KBYTE)
VCC(5.0) 4
2, 37,
43, 64
5V
VOLTAGE
REGULATORS
3.3 V
3.3 V
digital
supply
analog
supply
SYSTEM
CONTROLLER
CS0, CS1,
DREQ, DACK,
DA0*, DA1*, DA2 DIOR, DIOW
5
18, 17,
19, 20, 21
4
12, 13,
14, 15
DMA
HANDLER
DMA
INTERFACE
DMA
REGISTERS
11
16
22
40, 41,
44 to 57 16
19
20, 9 2
EOT
INTRQ
IORDY*
DATA0 to DATA15
BUS_CONF *
MODE0*, MODE1
MICRO-
CONTROLLER
HANDLER
ISP1581
MICRO
CONTROLLER
INTERFACE
22
38, 39, 30 to 35 8
25, 29, 26, 27 4
28
READY*
AD0 to AD7
CS, ALE/A0, (R/W)/RD,
DS/ WR
INT
1, 36, 42, 61
3, 23 4 24, 58
63 62
4
DGND
22
AGND
VCC(3.3)
Vreg (3.3)
SUSPEND WAKEUP
* Denotes shared pin usage
MGT234
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
Fig 1. Block diagram.

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Philips Semiconductors
6. Pinning information
6.1 Pinning
idth
ISP1581
USB 2.0 HS interface device
DGND 1
VCC(5.0) 2
AGND 3
Vreg(3.3) 4
D5
D+ 6
RPU 7
RREF 8
MODE1 9
RESET 10
EOT 11
DREQ 12
DACK 13
DIOR 14
DIOW 15
INTRQ 16
ISP1581BD
48 DATA6
47 DATA5
46 DATA4
45 DATA3
44 DATA2
43 VCC(5.0)
42 DGND
41 DATA1
40 DATA0
39 AD7
38 AD6
37 VCC(5.0)
36 DGND
35 AD5
34 AD4
33 AD3
MBL248
Fig 2. Pin configuration LQFP64.
9397 750 07648
Objective specification
Rev. 02 — 23 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
6.2 Pin description
Table 2: Pin description for LQFP64
Symbol [1]
Pin Type [2] Description
DGND
1-
digital ground
VCC(5.0)
AGND
2-
3-
supply voltage (3.3 or 5.0 V)
analog ground
Vreg(3.3)
5-
regulated supply voltage (3.3 V ± 10%) from internal
regulator; supplies internal analog circuits; used to connect
decoupling capacitor and 1.5 kpull-up resistor on D+ line
Remark: Cannot be used to supply external devices.
D5 AI/O USB Dconnection (analog)
D+ 6 AI/O USB D+ connection (analog)
RPU
RREF
7 AI
8 AI
connection for external pull-up resistor for USB D+ line;
must be connected to Vreg(3.3) via a 1.5 kresistor
connection for external bias resistor; must be connected to
ground via a 12.2 k(± 0.1%) resistor
MODE1
9I
selects function of pin ALE/A0 (in Split Bus mode only):
0 — ALE function (address latch enable)
1 — A0 function (address/data indicator).
RESET
10 I
Remark: Connect to VCC(5.0) in Generic Processor mode.
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset; connect to VCC for power-on reset
(internal POR circuit)
EOT
11 I
End Of Transfer input (programmable polarity, see
Table 37); used in DMA slave mode only
DREQ
12 I/O
DMA request (programmable polarity); direction depends
on the bit MASTER in the DMA Hardware register (DMA
master: input, DMA slave: output); see Table 37
DACK
13 I/O
DMA acknowledge (programmable polarity); direction of
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 37
DIOR
14 I/O
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 37
DIOW
15 I/O
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 37
INTRQ
16 I
interrupt request input from ATA/ATAPI peripheral
CS1
17 O
chip select output for ATAPI device
CS0
18 O
chip select output for ATAPI device
BUS_CONF/ 19
DA0
I/O
during power-up: input to select the bus configuration
0 — Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate 8/16-bit DMA data bus on DATA[15:0]
1 — Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit DMA data bus on DATA[15:0].
normal operation: address output to select the task file
register of an ATAPI device
9397 750 07648
Objective specification
Rev. 02 — 23 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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