ispGDX120A-5T176.pdf 데이터시트 (총 25 페이지) - 파일 다운로드 ispGDX120A-5T176 데이타시트 다운로드

No Preview Available !

ispGDXTM Family
In-System Programmable
Generic Digital CrosspointTM
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Three Device Options: 80 to 160 Programmable I/O
Pins
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
— PCI Compliant Output Drive
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
Slew Rate Control
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• ispGDX OFFERS THE FOLLOWING ADVANTAGES
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
I/O Pins D
ISP
Control
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
Boundary
Scan
Control
I/O Pins B
Description
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
ispgdx_08
1

No Preview Available !

Specifications ispGDX Family
Description (Continued)
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
found in each I/O cell. Each output has individual, pro-
grammable I/O tri-state control (OE), output latch clock
(CLK) and two multiplexer control (MUX0 and MUX1)
inputs. Polarity for these signals is programmable for
each I/O cell. The MUX0 and MUX1 inputs control a fast
4:1 MUX, allowing dynamic selection of up to four signal
sources for a given output. OE, CLK and MUX0 and
MUX1 inputs can be driven directly from selected sets of
I/O pins. Optional dedicated clock input pins give mini-
mum clock-to-output delays.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDX devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
source current and can be tied together in parallel for
greater drive. Programmable output slew rate can be
defined independently for each I/O pin to reduce overall
ground bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com-
mands or through Lattices industry-standard ISP protocol.
The BSCAN/ispEN pin is used to make this selection.
The ispGDX I/Os are designed to withstand live inser-
tionsystem environments. The I/O buffers are disabled
during power-up and power-down cycles. When design-
ing for live insertion,absolute maximum rating conditions
for the Vcc and I/O pins must still be met. For additional
information, an application note about using Lattice de-
vices in hot swap environments can be downloaded from
the Lattice web site at www.latticesemi.com.
Table 1. ispGDX Family Members
ispGDX DEVICE
ispGDX80A
ispGDX120A
ispGDX160/A
I/O Pins
I/O-OE Inputs*
I/O-Clk Inputs*
I/O-MUXsel1 Inputs*
80
20
20
20
120 160
30 40
30 40
30 40
I/O-MUXsel2 Inputs*
20
30
40
Dedicated Clock Pins
2
4
4
BSCAN / ispEN
111
TOE
1** 1
1
BSCAN / ISP Interface
4
4
4
RESET
111
Power/GND
12 25 33
Pin Count/Package
100-Pin TQFP
176-Pin TQFP/
160-Pin PQFP
208-Pin PQFP
272-Ball BGA
* The CLK, OE, MUX0 and MUX1 terminals on each I/O cell can each access 25% of the I/Os.
** MUXed with Y1.
2

No Preview Available !

Specifications ispGDX Family
Architecture
The ispGDX architecture is different from traditional PLD
architectures, in keeping with its unique application fo-
cus. The block diagram is shown below. The
programmable interconnect consists of a single Global
Routing Pool (GRP). Unlike ispLSI devices, there are no
programmable logic arrays on the device. Control signals
for OEs, Clocks and MUX Controls must come from
designated sets of I/O pins. The polarity of these signals
can be independently programmed in each I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
The in-system programming process uses either a Bound-
ary Scan based or Lattice ISP protocol. The programming
protocol is selected by the BSCAN/ispEN pin as de-
scribed later.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines called MUX0 and MUX1 as shown in
Figure 1. The four data inputs to the MUX (called MUXA,
MUXB, MUXC and MUXD) come from I/O signals found
in the GRP. Each MUX data input can access one quarter
of the total I/Os. For example, in a 160 I/O ispGDX, each
data input can connect to one of 40 I/O pins. MUX0 and
MUX1 can be driven by designated I/O pins called
MUXsel1 and MUXsel2. Each MUXsel input covers 25%
of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1
can be driven from either MUXsel1 or MUXsel2. The I/O
cell also includes a programmable flow-through latch or
register that can be placed in the input or output path and
bypassed for combinatorial outputs. As shown in Figure
1, when both register/latch control MUXes select the A
path, the register/latch gets its inputs from the 4:1 MUX
and drives the I/O output. When selecting the Bpath,
the register/latch is directly driven by the I/O input while
its output feeds the GRP. The programmable polarity
Clock to the latch or register can be connected to any
I/O in the I/O-Clock set (one-quarter of total I/Os) or to
one of the dedicated clock input pins (Yx). Use of the
dedicated clock inputs gives minimum clock-to-output
delays and minimizes delay variation with fanout. Com-
binatorial output mode may be implemented by a
dedicated architecture bit and bypass MUX. I/O cell
output polarity can be programmed as active high or
active low.
Figure 1. ispGDX I/O Cell and GRP Detail (160 I/O Device)
I/O 0
I/O 1
Logic "1" 160 I/O Inputs
E2CMOS
Programmable
Interconnect
•••
•••
I/O 80
I/O 81
4-to-1 MUX
MUXA
MUXB
MUXC
MUXD
MUX0 MUX1
•••
Bypass Option
Register
A or Latch
BD
Q
CLK
Reset
I/O Cell N
Prog.
Pull-up
C I/O Pin
R
Programmable
Slew Rate
Boundary
Scan Cell
I/O MUX Operation
MUX1 MUX0 DATA INPUT SELECTED
00
MUXA
01
MUXB
11
MUXC
10
MUXD
I/O 78
I/O 79
80 I/O Cells
••••••
160 Input GRP
Inputs Vertical Y0-Y3
Outputs Horizontal Global
Clocks
Global
Reset
I/O 158
I/O 159
80 I/O Cells
3

No Preview Available !

Specifications ispGDX Family
Applications
The ispGDX family architecture has been developed to
deliver an in-system programmable signal routing solu-
tion with high speed and high flexibility. The devices are
targeted for three similar but distinct classes of end-
system applications:
Programmable, Random Signal Interconnect (PRSI)
This class includes PCB-level programmable signal rout-
ing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of program-
mable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control in-
puts.
Programmable Data Path (PDP)
This application area includes system data path trans-
ceiver, MUX and latch functions. With todays 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of on-boardbus and memory inter-
faces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to inte-
grate these on-board data path functions in an analogous
way to programmable logics solution to control logic
integration. Lattices ispLSI High-Density PLDs make an
ideal control logic complement to the ispGDX in-system
programmable data path devices as shown below.
Figure 2. ispGDX Complements Lattice ispLSI
Address
Inputs
(from µP)
Control
Inputs
(from µP)
Data Path
Bus #1
State Machines
ispLSI Device
Control
Outputs
Buffers / Registers
ispGDX Device
ISP/JTAG
Interface
Decoders
System
Clock(s)
Buffers / Registers
Data Path
Bus #2
Configuration
(Switch)
Outputs
Programmable Switch Replacement (PSR)
Includes solid-state replacement and integration of me-
chanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDX devices can
be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDX device will interface
with control logic outputs from other components (such
as ispLSI) on the board (which frequently change late in
the design process as control logic is finalized), there
must be no restrictions on pin-to-pin signal routing for this
type of application.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the pro-
grammable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architec-
ture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin re-
routing is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
As a result, the ispGDX architecture has been defined to
support PSR and PRSI applications (including bidirec-
tional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designers needs.
The following diagrams illustrate several ispGDX appli-
cations.
4

No Preview Available !

Specifications ispGDX Family
Applications (Cont.)
Figure 3. Address Demultiplex/Data Buffering
XCVR
I/OA I/OB
OEA OEB
Address
Latch
DQ
CLK
Buffered
Data
To Memory/
Peripherals
Address
Figure 4. Data Bus Byte Swapper
D0-7
XCVR
I/OA I/OB
OEA OEB
D8-15
XCVR
I/OA I/OB
OEA OEB
D0-7
XCVR
I/OA I/OB
OEA OEB
D8-15
XCVR
I/OA I/OB
OEA OEB
Figure 5. Four-Port Memory Interface
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Memory
Port
Port #2
OE2
OEM
Port #3
OE3
SEL0
Port #4
OE4
SEL1
To
Memory
Designing with the ispGDX
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-19 (80 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restric-
tions are reasonable in order to optimize speed and cost.
User Electronic Signature
The ispGDX Family includes dedicated User Electronic
Signature (UES) E2CMOS storage to allow users to code
design-specific information into the devices to identify
particular manufacturing dates, code revisions, or the
like. The UES information is accessible through the
boundary scan or Lattice ISP programming port via a
specific command. This information can be read even
when the security cell is programmed.
Security Bit
The ispGDX Family includes a security bit feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Note: All OE and SEL lines driven by external arbiter logic (not shown).
5