J176.pdf 데이터시트 (총 2 페이지) - 파일 다운로드 J176 데이타시트 다운로드

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P-Channel JFET Switch
CORPORATION
J174 – J177 / SST174 – SST177
FEATURES
Low Insertion Loss
No Offset or Error Generated By Closed Switch
- Purely Resistive
- High Isolation Resistance From Driver
Short Sample and Hold Aperture Time
•• Fast Switching
APPLICATIONS
Analog Switches
Choppers
•• Commutators
PIN CONFIGURATION
TO-92
DGS
5508
SOT-23
G
D
S
PRODUCT MARKING (SOT-23)
SST174
P04
SST175
P05
SST176
P06
SST177
P07
ABSOLUTE MAXIMUM RATINGS
(TA = 25oC unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 30V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC
Operating Temperature Range . . . . . . . . . . . -55oC to +135oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . . 300oC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350mW
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part
Package
Temperature Range
J174-J177
Plastic TO-92
SST174-SST177 Plastic SOT-23
-55oC to +135oC
-55oC to +135oC
For Sorted Chips in Carriers see 2N5114 series.

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CORPORATION
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
SYMBOL PARAMETER
J174
J175
J176
J177
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
TEST CONDITIONS
Gate Reverse
IGSS
Current
1 1 1 1 nA VDS = 0, VGS = 20V
(Note 1)
VGS(off)
BVGSS
Gate Source
Cutoff Voltage
Gate Source
Breakdown
Voltage
5
30
10 3
30
61
30
4 0.8
30
2.25
VDS = -15V, ID = -10nA
V
VDS = 0, IG = 1µA
Drain
IDSS
Saturation
Current
-20
-135 -7
(Note 2)
-70 -2
-35 -1.5
-20 mA VDS = -15V, VGS = 0
ID(off)
Drain Cutoff
Current
(Note 1)
-1 -1 -1 -1 nA VDS = -15V, VGS = 10V
rDS(on)
Drain-Source
ON Resistance
85
125 250 300 VGS = 0, VDS = -0.1V
Drain-Gate
Cdg(off) OFF
5.5 5.5 5.5 5.5
Capacitance
VDS = 0,
Source-Gate
VGS = 10V
Csg(off) OFF
5.5 5.5 5.5 5.5 pF
f = 1MHz (Note 3)
Capacitance
Drain-Gate
Cdg(on) Plus Source
+ Csg(on) Gate ON
32
32
32
32
Capacitance
VDS = VGS = 0
td(on)
Turn On Delay
Time
2
5 15
tr Rise Time
5
10 20
td(off)
Turn Off Delay
Time
5
10 15
tf Fall Time 10 20 20
NOTES: 1. Approximately doubles for every 10oC increase in TA.
2. Pulse test duration -300µs; duty cycle 3%.
3. For design reference only, not 100% tested.
20 Switching Time Test Conditions
(Note 3)
25
ns VDD
J174 J175 J176 J177
-10V -6V -6V -6V
20
VGS(off) 12V
8V
3V
3V
RL 56012k5.6k10k
VGS(on) 0V 0V 0V 0V
25