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DISCRETE SEMICONDUCTORS
DATA SHEET
J174; J175;
J176; J177
P-channel silicon field-effect
transistors
Product specification
File under Discrete Semiconductors, SC07
April 1995

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Philips Semiconductors
P-channel silicon field-effect transistors
Product specification
J174; J175;
J176; J177
DESCRIPTION
Silicon symmetrical p-channel
junction FETs in a plastic TO-92
envelope and intended for application
with analog switches, choppers,
commutators etc.
A special feature is the
interchangeability of the drain and
source connections.
PINNING
1 = source
2 = gate
3 = drain
Note: Drain and source are
interchangeable.
handbook, half1pa2ge
3
g
MAM388
d
s
Fig.1 Simplified outline and symbol, TO-92.
QUICK REFERENCE DATA
Drain-source voltage
Gate-source voltage
Gate current
Total power dissipation
up to Tamb = 50 °C
Drain current
VDS = 15 V; VGS = 0
Drain-source ON-resistance
VDS = 0.1 V; VGS = 0
± VDS
VGSO
IG
max.
max.
max.
30
30
50
V
V
mA
Ptot
IDSS
max.
min.
max.
400
J174
20
135
J175
7
70
J176
2
35
mW
J177
1.5 mA
20 mA
RDS on max.
85
125
250
300
April 1995
2

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Philips Semiconductors
P-channel silicon field-effect transistors
Product specification
J174; J175;
J176; J177
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Gate-source voltage
Gate-drain voltage
Gate current (DC)
Total power dissipation
± VDS
VGSO
VGDO
IG
up to Tamb = 50 °C
Storage temperature range
Junction temperature
Ptot
Tstg
Tj
max.
max.
max.
max.
max.
max.
30 V
30 V
30 V
50 mA
400
65 to +150
150
mW
°C
°C
THERMAL RESISTANCE
From junction to ambient in free air
Rth j-a
=
250 K/W
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Gate cut-off current
VGS = 20 V; VDS = 0
Drain cut-off current
VDS = 15 V; VGS = 10 V
Drain current
VDS = 15 V; VGS = 10 V
Gate-source breakdown voltage
IG = 1 µA; VDS = 0
Gate-source cut-off voltage
ID = 10 nA; VDS = 15 V
Drain-source ON-resistance
VDS = 0.1 V; VGS = 0
J174 J175 J176 J177
IGSS
IDSX
IDSS
max.
11
1 1 nA
max.
11
1 1 nA
min.
max.
20 7
135 70
2 1.5 mA
35 20 mA
V(BR)GSS min.
VGS off
min.
max.
30 30 30 30 V
53
10 6
1 0.8 V
4 2.25 V
RDSon
max.
85 125 250 300
April 1995
3

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Philips Semiconductors
P-channel silicon field-effect transistors
DYNAMIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Input capacitance, f = 1 MHz
VGS = 10 V; VDS = 0 V
VGS = VDS = 0
Feedback capacitance, f = 1 MHz
VGS = 10 V; VDS = 0 V
Switching times (see Fig.2 + 3)
Delay time
Rise time
Turn-on time
Storage time
Fall time
Turn-off time
Test conditions:
Cis
Cis
Crs
td
tr
ton
ts
tf
toff
VDD
VGS off
RL
VGS on
Product specification
J174; J175;
J176; J177
typ. 8
typ. 30
pF
pF
typ. 4
pF
J174 J175 J176 J177
typ. 2 5 15 20 ns
typ. 5 10 20 25 ns
typ. 7 15 35 45 ns
typ. 5 10 15 20 ns
typ. 10 20 20 25 ns
typ. 15 30 35 45 ns
10 6
12 8
560 1200
00
6 6V
6 3V
2000 2900
0 0V
handbook, halfpage
VDD
50
Vout
RL
Vin
50
D.U.T
MBK292
Fig.2 Switching times test circuit.
VGSoff
INPUT
10%
OUTPUT
10%
90%
tf
ts
90%
10%
90%
tr
td MBK293
Fig.3 Input and output waveforms;
td + tr = ton ; ts + tf = toff.
April 1995
4

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Philips Semiconductors
P-channel silicon field-effect transistors
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads
Product specification
J174; J175;
J176; J177
SOT54
c
E
d
1
2
D
3
b1
AL
L1
b
e1
e
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A b b1 c D d E e e1 L L1(1)
mm
5.2
5.0
0.48 0.66 0.45
0.40 0.56 0.40
4.8
4.4
1.7
1.4
4.2
3.6
2.54
1.27
14.5
12.7
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
EUROPEAN
PROJECTION
SOT54
TO-92
SC-43
ISSUE DATE
97-02-28
April 1995
5