The oscillator in the SG1524 uses an external resistor RT to
establish a constant charging current into an external capacitor
CT. While this uses more current than a series-connected RC, it
provides a linear ramp voltage at CT which is used as a time-
dependent reference for the PWM comparator. The charging
current is equal to 3.6V/RT, and should be restricted to between
30µA and 2mA. The equivalent range for RT is 1.8K to 100K.
The range of values for CT also has limits, as the discharge time
of CT determines the pulse width of the oscillator output pulse.
The pulse is used (among other things) as a blanking pulse to
both outputs to insure that there is no possibility of having both
outputs on simultaneously during transitions. This output
deadtime relationship is shown in Figure 1. A pulse width below
0.35 microseconds may cause failure of the internal flip-flop to
toggle. This restricts the minimum value of CT to 1000pF. (Note:
Although the oscillator output is a convenient oscilloscope sync
input, the probe capacitance will increase the pulse width and
decrease the oscillator frequency slightly.) Obviously, the upper
limit to the pulse width is determined by the modulation range
required in the power supply at the chosen switching frequency.
Practical values of CT fall between 1000pF and 0.1µF, although
successful 120 Hz oscillators have been implemented with val-
ues up to 5µF and a series surge limit resistor of 100 ohms.
The oscillator frequency is approximately 1/RT•CT; where R is in
ohms, C is in microfarads, and the frequency is in Megahertz. For
greater accuracy, the chart in Figure 2 may be used for a wide
range of operating frequencies.
Note that for buck regulator topologies, the two outputs can be
wire-ORed for an effective 0-90% duty cycle range. With this
connection, the output frequency is the same as the oscillator
frequency. For push-pull applications, the outputs are used
separately; the flip-flop limits the duty cycle range at each output
to 0-45%, and the effective switching frequency at the trans-
former is 1/2 the oscillator frequency.
If it is desired to synchronize the SG1524 to an external clock, a
positive pulse may be applied to the clock pin. The oscillator
should be programmed with RT and CT values that cause it to free-
run at 90% of the external sync frequency. A sync pulse with a
maximum logic 0 of +0.3 volts and a minimum logic 1 of +2.4 volts
applied to Pin 3 will lock the oscillator to the external source. The
minimum sync pulsewidth should be 200 nanoseconds, and the
maximum is determined by the required deadtime. The clock pin
should never be driven more negative than -0.3 volts, nor more
positive than +5.0 volts. The nominal resistance to ground is
3.2K at the clock pin, ±25% over temperature.
If two or more SG1524s must be synchronized together, program
one master unit with RT and CT for the desired frequency. Leave
the RT pins on the slaves open, connect the CT pins to the CT of
the master, and connect the clock pins to the clock pin of the
master. Since CT is a high-impedance node, this sync technique
works best when all devices are close together.
FIGURE 1 - OUTPUT STAGE DEADTIME VS. CT
FIGURE 2 - OSCILLATOR FREQUENCY VS. RT AND CT
4/90 Rev 1.1 2/94
Copyright © 1994
LINFINITY Microelectronics Inc.
4 11861 Western Avenue ∞ Garden Grove, CA 92841
(714) 898-8121 ∞ FAX: (714) 893-2570