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S3C8618/C8615/P8615
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C8618/C8615/P8615 MICROCONTROLLERS
The S3C8618/C8615/P8615 single-chip 8-bit
microcontroller is based on the powerful SAM8 CPU
architecture. The internal register file is logically
expanded to increase the on-chip register space. The
S3C8618/C8615/P8615 have 8/16 K bytes of on-chip
program ROM.
Following Samsung's modular design approach, the
following peripherals were integrated with the SAM8
core:
— Four programmable I/O ports (total 28 pins)
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One 8-bit counter with selectable clock sources,
including Hsync or Csync input
— One 8-bit timer for interval mode
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
— Multi master IIC-bus with DDC support.
The S3C8618/C8615/P8615 are a versatile
microcontroller that is ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, and multi-master IIC-bus support
with DDC. It is available in a 42-pin SDIP or a 44-pin
QFP package.
Figure 1-1. S3C8618/C8615/P8615
Microcontrollers
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PRODUCT OVERVIEW
S3C8618/C8615/P8615
FEATURES
CPU
• SAM8 CPU core
Memory
• 8/16-Kbyte internal program memory (ROM)
• 272-byte general-purpose register area
Instruction Set
• 78 instructions
• IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
• 500 ns minimum (with 12 MHz CPU clock)
Interrupts
• Nine interrupt sources
• Nine interrupt vectors
• Six interrupt levels
• Fast interrupt processing for a select level
General I/O
• Four I/O ports (total 28 pins):
8-Bit Basic Timer
• Programmable timer for oscillation stabilization
interval control or watchdog timer functions
• Three selectable internal clock frequencies
Timer/Counters
• One 8-bit general-purpose timer/counter with
programmable operating modes and the following
clock source options:
— Two selectable internal clock frequencies
• One 8-bit timer with interval operating mode
• One 8-bit counter with the following clock source
options:
— Two selectable internal clock frequencies
— Hsync (or Csync) input from the sync
processor block
— External clock source
Pulse Width Modulator
• Seven 8-bit PWM modules:
— 8-bit basic frame
— Four push-pull and three n-channel,
open-drain output channels
— Selectable clock frequencies: 46.875 kHz at
12 MHz fosc.
Sync Processor
• Detection of sync input signals (Vsync-I, Hsync-I,
and Csync-I)
• Sync signal separation and output (Hsync-O,
Vsync-O, and Clamp-O)
• Pseudo sync signal output
• Programmable clamp signal output
DDC and Multi-Master IIC-Bus
• Serial peripheral interface
• Support for display data channel (DDC)
Oscillator Frequency
• 6 MHz to 12 MHz external crystal oscillator
• Interval Max. 12MHz CPU clock
Operating Temperature Range
• – 40°C to + 85°C
Operating Voltage Range
• 4.5 V to 5.5 V
Package Types
• 42-pin SDIP, 44-pin QFP
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S3C8618/C8615/P8615
BLOCK DIAGRAM
PRODUCT OVERVIEW
P0.0–P0.7/INT0-INT2
P2.0–P2.7
RESET
INT0-INT2
XIN
XOUT
MAIN
OSC
PWM0
PWM1
PWM6
8-BIT
PWM
(7-CH)
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
T0CAP
SYNC
PRO-
CESSOR
TIMER 0
PORT 0
PORT 2
INTERNAL BUS
I/O PORT and INTERRUPT
CONTROL
SAM8 CPU
8/16-KBYTE MASK ROM
272-BYTE REGISTER FILE
8-blt
Counter
(TIMER 1)
T1CK
Interval
timer
(TIMER 2)
TEST
PORT 1
P1.0–P1.3
PORT3
P3.0–P3.7
DDC and
Multi master
IIC-bus
SCL
SDA
Figure 1-2. Block Diagram
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PRODUCT OVERVIEW
PIN ASSIGNMENTS
S3C8618/C8615/P8615
P3.1
P3.0
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/T0CAP
P0.5/T1CK
VDD
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C8618/8615
42-SDIP
(Top View)
42 P3.2
41 VSS2
40 P3.3
39 P3.4
38 P3.5
37 P3.6
36 P3.7
35 RESET
34 XOUT
33 XIN
32 VSS1
31 P2.7/Csync-I
30 Hsync-I
29 Vsync-I (VCLK)
28 Clamp-O
27 Hsync-O
26 Vsync-O
25 SCL
24 SDA
23 TEST
22 P2.6/PWM6
Figure 1-3. Pin Assignment Diagram (42-SDIP Package)
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S3C8618/C8615/P8615
PRODUCT OVERVIEW
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
N.C.
P2.6/PWM6
TEST
SDA
SCL
Vsync-O
34
35
36
37
38
39
40
41
42
43
44
S3C8618/8615
44-QFP
(Top View)
33 P0.2/INT2
32 P0.1/INT1
31 P0.0/INT0
30 P3.0
29 P3.1
28 NC
27 P3.2
26 VSS2
25 P3.3
24 P3.4
23 P3.5
Figure 1-4. Pin Assignment Diagram (44-QFP Package)
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