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®
PRELIMINARY
Data Sheet
October 2003
ISL6413
FN9129
Triple Output Regulator with Single
Synchronous Buck and Dual LDO
The ISL6413 is a highly integrated triple output regulator
which provides a single chip solution for wireless chipset
power management. The device integrates high efficiency
synchronous buck regulator with two ultra low noise LDO
regulators. The IC accepts an input voltage range of 3.0V to
3.6V and provides three regulated output voltages: 1.8V
(PWM), 2.84V (LDO1), and another ultra-clean 2.84V
(LDO2).
The Synchronous current mode PWM regulator with
integrated N- and P-channel power MOSFET provides pre-
set 1.8V for BBP/MAC core supply. Synchronous
rectification with internal MOSFETs is used to achieve higher
efficiency and reduced number of external components.
Operating frequency is typically 750kHz allowing the use of
smaller inductor and capacitor values. The device can be
synchronized to an external clock signal in the range of
500kHz to 1MHz. The PG_PWM output indicates loss of
regulation on PWM output.
The ISL6413 also has two LDO regulators which use an
internal PMOS transistor as the pass device. LDO2 features
ultra low noise that does not typically exceed 30µV RMS to
aid VCO stability. The EN_LDO pin controls LDO1 and
LDO2 outputs. The ISL6413 also integrates a RESET
function, which eliminates the need for additional RESET IC
required in WLAN applications. The IC asserts a RESET
signal whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for at least 25ms after VIN has
risen above the reset threshold. The PG_LDO output
indicates loss of regulation on either of the two LDO outputs.
Other features include over current protection for all three
outputs and thermal shutdown.
High integration and the thin Quad Flat No-lead (QFN)
package makes ISL6413 an ideal choice to power many of
today’s small form factor industry standard wireless cards
such as PCMCIA, mini-PCI and Cardbus-32.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. #
ISL6413IR
-40 to 85
24 Ld QFN L24.4x4B
Features
• Fully Integrated Synchronous Buck Regulator + Dual LDO
• High Output Current (For QFN package)
- PWM, 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
- LDO1, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
- LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
• Ultra-Compact DC-DC Converter Design
• Stable with Small Ceramic Output Capacitors
• High conversion efficiency
• Low Shutdown supply current
• Ultra-Low Dropout Voltage for LDOs
- LDO1, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA
- LDO2, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA
• Ultra-Low Output Voltage Noise
- <30µVRMS (typ.) for LDO2 (VCO Supply)
• PG_LDO, PG_PWM and PG_PWM outputs
• Extensive circuit protection and monitoring features
- Over voltage protection
- Over current protection
- Shutdown
- Thermal Shutdown
• Integrated RESET output for microprocessor reset
• Proven Reference Design for Total WLAN System
Solution
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint Improves PCB
Efficiency and Is Thinner in Profile
Applications
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Liberty Chipset
• Hand-Held Instruments
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6413
ISL6413 (QFN)
TOP VIEW
24 23 22 21 20 19
PG_PWM 1
18 VOUT
PG_PWM 2
17 CC2
SYNC 3
16 VOUT2
NC 4
15 GND_LDO
EN_PWM 5
14 VOUT1
PG_LDO 6
13 CC1
7 8 9 10 11 12
Typical Application Schematic
3.3V
3.3V
C10
10µF
C8
0.1µF
C9
1.0µF
L1
10µH
C7
10µF
1.8V
R1 10K
24 23 22 21 20 19
PG_PWM
PG_PWM
1
2
18 VOUT
17 CC2
C6 33nF
SYNC
NC
3
4
ISL6413
16 VOUT2
15 GND_LDO
C4
10µF
EN
5
R3 PG_LDO 6
14 VOUT1
13 CC1
C3 10µF
10K
7 8 9 10 11 12
C2 33nF
2.84V
2.84V
NOTE: All capacitors are ceramic.
C1
10nF
C5 4.7µF
3.3V
2

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Functional Block Diagram
CT
RESET
RESET
PG_LDO
RESET
POR POR
ISL6413
BAND
GAP
REF
1.2V
WINDOW
COMP.
Gm
VIN_LDO
EN_LDO
EN
CONTROL
LOGIC
GND_LDO
THERMAL
SHUTDOWN
150oC
Gm
WINDOW
COMP.
+-
LDO1
+-
LDO2
VIN_LDO
VIN_LDO
OUT1
CC1
CC2
OUT2
VIN
SGND
SOFT
START
SLOPE
COMPENSATION
EA GM
EN
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
COMPENSATION
VIN
SYNC EN
750kHz
OSCILLATOR
POWER GOOD
PWM
VOUT
UVLO
PWM
REFERENCE
0.45V
PG_PWM
ANTI-RINGING
PG_PWM
3
CURRENT
SENSE
GATE
DRIVE
ZERO
CURRENT
DETECT
PVCC
LX VOUT
PGND
GND
VOUT

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ISL6413
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C)
SYMBOL
A
A1
A2
A3
b
D
D1
MILLIMETERS
MIN
NOMINAL
MAX
0.80 0.90 1.00
- - 0.05
- - 1.00
0.20 REF
0.18 0.23 0.30
4.00 BSC
3.75 BSC
NOTES
-
-
9
9
5, 8
-
9
D2 2.19 2.34 2.49 7, 8
E
4.00 BSC
-
E1 3.75 BSC 9
E2 2.19 2.34 2.49 7, 8
e
0.50 BSC
-
k 0.25
-
--
L 0.30 0.40 0.50 8
L1 -
- 0.15 10
N 24 2
Nd 6 3
Ne 6 3
P-
- 0.60 9
θ-
- 12 9
Rev. 0 10/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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