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®
Data Sheet
May 2002
ISL6444
FN9069.1
Dual PWM Controller with DDR Memory
Option for Gateway Applications
The ISL6444 PWM controller provides high efficiency and
regulation for two output voltages adjustable in the range from
0.9V to 5.5V that are required to power I/O, chip-sets, and
memory banks in high-performance notebook computers,
PDAs, and Internet appliances.
Synchronous rectification and hysteretic operation at light
loads contribute to a high efficiency over a wide range of
loads. The hysteretic mode of operation can be disabled
separately on each PWM converter if continuous conduction
operation is desired for all load levels. Efficiency is even
further enhanced by using MOSFET’s RDS(ON) as a current
sense component.
Feed-forward ramp modulation, current mode control
scheme, and internal feed-back compensation provide fast
response to load transients. Out-of-phase operation with a
180o phase shift reduces the input current ripple.
The controller can be transformed in a complete DDR
memory power supply solution by activating a DDR pin. In
DDR mode of operation one of the channels tracks the
output voltage of another channel and provides output
current sink and source capability–features essential for
proper powering of DDR chips. The buffered reference
voltage required by this type of memory is also provided.
The ISL6444 monitors the output voltages. Each PWM
controller generates a PGOOD (power good) signal when
the soft-start is completed and the output is within ±10% of
the set point.
A built-in overvoltage protection prevents output voltage
from going above 115% of the set point. Normal operation
automatically restores when the overvoltage conditions go
away. Undervoltage protection latches the chip off when
either output drops below 75% of its set value after the soft-
start sequence for this output is completed. An adjustable
overcurrent function monitors the output current by sensing
the voltage drop across the lower MOSFET. If precision
current-sensing is required, an external current-sense
resistor may optionally be used.
The IC comes in a 28 lead SSOP package.
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6444CA
-10 to 85 28 Ld SSOP
ISL6444CA-T
-10 to 85
28 Ld SSOP
Taped and
Reeled
PKG. NO.
M28.15
M28.15
Features
• Provides regulated output voltage in the range 0.9V–5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET’s RDS(ON)
- Optional current-sense resistor for precision overcurrent
• Undervoltage lock-out on VCC pin
• Dual mode operation
- Operates directly from battery 5.0-24V input
- Operates from 3.3V or 5V system rail
• Excellent dynamic response
- Combined voltage feed-forward and current mode
control
• Power-good signal for each channel
• 300kHz switching frequency
- Out-of-phase operation for reduced input ripple
- In-phase operation in DDR mode for reduced channel
interference
- Out-of-phase operation with 90o phase shift for two-
stage conversion in DDR mode
Applications
Residential and Enterprise Gateways
• DSL Modems
• Routers and Switchers
Pinout
ISL6444 (SSOP-28)
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
1
2
3
4
5
6
7
8
VOUT1 9
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 VOUT2
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

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Generic Application Circuits
OCSET1
PWM1
ISL6444
+VIN =+5V... +24V
Q1
L1
Q2
C1
VOUT1
(+1.8V)
OCSET2
PWM2
DDR
Q3 VOUT2
L2
(+1.2V)
Q4
C2
ISL6444 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
+5V
DDR
OCSET1
PWM1
VOUT3
DDR REF
(+1.25V)
PGOOD2/REF
PWM2
+VIN +5V...24V
Q1
L1
Q2
C1
OCSET2
Q3
Q4
VOUT1
VDDQ
(+2.5V)
R
R
VOUT2
L2 VTT
(+1.25V)
C2
ISL6444 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
2

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ISL6444
Absolute Maximum Ratings
Bias Voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V
PHASE, BOOT, ISEN, UGATE . . . . . . . . . . . . . GND-0.3V to +33.0V
BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to Vcc + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Bias Voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V ±5%
Input Voltage, Vin . . . .
Ambient Temperature
......
Range.
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+5.0V to +24.0V
. -10oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -10oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
VCC SUPPLY
Bias Current
ICC LGATEx, UGATEx Open, VSENx forced above -
regulation point, DDR=0, VIN>5V
Shut-down Current
VCC UVLO
ICCSN
-
Rising Vcc Threshold
Falling Vcc Threshold
VIN
VCCU
VCCD
4.3
4.1
Input Voltage Pin Current (Sink)
Input Voltage Pin Current (Source)
Shut-down Current
OSCILLATOR
IVIN
IVINO
IVINS
10
-
-
PWM1 Oscillator Frequency
Ramp Amplitude, pk-pk
Ramp Amplitude, pk-pk
Ramp Offset
Ramp/VIN Gain
Ramp/VIN Gain
REFERENCE AND SOFT START
Fc
VR1
VR2
VROFF
GRB1
GRB2
Vin= 16V, by design
Vin= 5V, by design
By design
Vin3V, by design
1 ≤ Vin 3V, by design
255
-
-
-
-
-
Internal Reference Voltage
Reference Voltage Accuracy
VREF
-
-1.0
Soft-Start Current During Start-up
Soft-Start Complete Threshold
PWM CONVERTERS
ISOFT
VST
By design
-
Load Regulation
VSEN pin bias current
VOUT pin input impedance
IVSEN
IVOUT
0.0mA < IVOUT1 < 5.0A; 5.0V < VBATT < 24.0V -2.0
By design
50
VOUT = 5V
40
TYP
2.2
-
4.65
4.35
-
-15
-
300
2
1.25
0.5
125
250
0.9
-
-5
1.5
-
80
55
MAX
3.2
30
4.75
4.45
30
-30
1
345
-
-
-
-
-
-
+1.0
-
+2.0
120
65
UNITS
mA
µA
V
V
µA
µA
µA
kHz
V
V
V
mV/V
mV/V
V
%
µA
V
%
nA
kOhm
3

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ISL6444
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Undervoltage Shut-Down Level
Overvoltage Shut-Down
GATE DRIVERS
VUVL
VOVP1
Fraction of the set point; ~2µs noise filter
Fraction of the set point; ~2µs noise filter
70 85
110 - 130
%
%
Upper Drive Pull-Up Resistance
R2UGPUP
Upper Drive Pull-Down Resistance
R2UGPDN
Lower Drive Pull-Up Resistance
R2LGPUP
Lower Drive Pull-Down Resistance
R2LGPDN
POWER GOOD AND CONTROL FUNCTIONS
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
- 8 15
- 3.2 5
- 8 15
- 1.8 3
Power Good Lower Threshold
Power Good Higher Threshold
VPG-
VPG+
Fraction of the set point; ~3µs noise filter
Fraction of the set point; ~3µs noise filter.
Guaranteed by design.
-13 -
-7
12 - 16
%
%
PGOODx Leakage Current
PGOODx Voltage Low
EN - Low (Off)
IPGLKG
VPGOOD
VPULLUP = 5.5V
IPGOOD = -4mA
- - 1 µA
- 0.5 0.85 V
-
- 0.8
V
EN - High (On)
2.5 -
-
V
CCM Enforced (Hysteretic Operation
Inhibited)
VOUTX pulled low
-
- 0.1
V
Automatic CCM/Hysteretic Operation Enabled
VOUTX connected to the output
0.9 -
-
V
DDR - Low (Off)
-
- 0.8
V
DDR - High (On)
2.5 -
-
V
DDR REF Output Voltage
DDR REF Output Current
VDDREF DDR=1, IREF=0...10mA
IDDREF DDR=1. Guaranteed by design.
0.99*
VOC2
-
VOC2
10
1.01*
VOC2
16
V
mΑ
4

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Block Diagram
BOOT1
UGATE1
PHASE1
UG1
OVP1
HI
LGATE1
PGND1
GATE
CONTROL
VCC
LG1
OVP1
GATE LOGIC
LO
MODE CHANGE COMP 1
-
HYST COMP 1
-
SOFT1 EN1 EN2 SOFT2
REFERENCE
AND
SOFT START
SDWN1
SDWN2
REF=0.9V
UG2
HI
OVP2
GATE LOGIC
LO
GATE
CONTROL
VCC
LG2
OVP2
MODE CHANGE COMP 2
-
HYST COMP 2
-
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
VSEN1
VREF
ISEN1
EA1
--
Σ-
LGATE1
LGATE1
- CSA1
OC COMP1
- OC LOGIC1
-Σ
EA2
--
OC COMP2
OC LOGIC2
-
LGATE2
CSA2
-
S2e
LGATE2
VCC
GND
VSEN1 OVP1
OUTPUT
VOLTAGE
MONITOR
PG1
OCSET1
1.24V
RAMP 1
ϕ=90o
S1
S2a
ϕ=0o CLK ϕ=180o RAMP 2
S2b VCC
VIN
1.24V
S2c
OVP2 VSEN2
OUTPUT
VOLTAGE
MONITOR
-
S2d
OCSET2
PG2/REF
VSEN2
ISEN2
DDR