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®
Data Sheet
ISL6504, ISL6504A
July 2003
FN9062.1
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6504 and ISL6504A complement other power
building blocks (voltage regulators) in ACPI-compliant
designs for microprocessor and computer applications. The
IC integrates three linear controllers/regulators, switching,
monitoring and control functions into a 16-pin wide-body
SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A
operating mode (active outputs or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6504 5VDUAL output is shut down. In the ISL6504A, the
5VDUAL output stays on during S4/S5 sleep states. This is
the only difference between the two parts; see Table 1.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element. Another internal regulator outputs a 1.5VSB
chip-set standby supply, which uses the 3V3DL pin as input
source for its internal pass element. The 3.3VDUAL/3.3VSB
and 1.5VSB outputs are active for as long as the ATX 5VSB
voltage is applied to the chip.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6504CB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504CR
0 to 70 20 Ld QFN
L20.6x6
ISL6504EVAL1 Evaluation Board
ISL6504ACB
0 to 70 16 Ld Wide SOIC M16.3
ISL6504ACR
0 to 70 20 Ld QFN
L20.6x6
ISL6504AEVAL1 Evaluation Board
Coming soon
0 to 70 16 Ld Narrow SOIC M16.15
Features
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- 1.5VSB ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
Applications
ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5VDUAL is shut down in S4/S5 sleep states
- ISL6504A: 5VDUAL stays on in S4/S5 sleep states
Pinouts
ISL6504/A (WIDE BODY SOIC)
TOP VIEW
1V5SB 1
3V3DLSB 2
3V3DL 3
1V2VID 4
3V3 5
S3 6
S5 7
GND 8
16 5VSB
15 VID_CT
14 VID_PG
13 SS
12 5VDL
11 5VDLSB
10 DLA
9 FAULT
NOTE: SOIC layout should accomodate both wide and narrow footprints.
ISL6504/A (6 X 6 QFN)
TOP VIEW
3V3DL 1
NC 2
1V2VID 3
3V3 4
S3 5
20 19 18 17 16
15 VID_PG
14 SS
13 NC
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at
GND potential. It can be left unconnected, or connected to GND; do NOT
connect to another potential.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
3V3DLSB
EA4
1V5SB
EA3 +
-
TO UV
DETECTOR
FAULT
UV DETECTOR
10mA
UV COMP
+
4.10V
-
5VDL GND
SS
3V3DL
3V3
5VSB DLA 5VDLSB
5VSB POR
4.4V/3.4V
3V3 MONITOR
2.75V/2.60V
TEMPERATURE
MONITOR
(TMON)
MONITOR AND CONTROL
+
1.265V
-
TO
UV DETECTOR
+ EA3
-
TO 3V3
+
-
10mA
S3 S5
FIGURE 1.
VID_CT
1V2VID
VID_PG

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ISL6504, ISL6504A
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
1.5VSB
1.5V
Q2
3.3VDUAL /3.3VSB
3.3V
FAULT
Q3
LINEAR
REGULATOR
LINEAR
CONTROLLER
LINEAR
REGULATOR
ISL6504/A
CONTROL
LOGIC
SHUTDOWN
SX
2
FIGURE 2.
1.2VVID
1.2V
VID_PG
Q4
Q5
5VDUAL
5V
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
VOUT1
1.5VSB
COUT1
Q1
VOUT3
3.3VDUAL/3.3VSB
FAULT
SLP_S3
SLP_S5
Q2
COUT3
SHUTDOWN
3
1V5SB
RDLA
3V3DLSB
3V3DL
FAULT
S3
S5
SS
CSS
3V3 5VSB
1V2VID
VID_CT
CCT_VID
COUT2
VOUT2
1.2VVID
ISL6504/A
VID_PG
5VDLSB
DLA
5VDL
Q4
COUT4
VID PGOOD
Q3
VOUT4
5VDUAL
GND
FIGURE 3.

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ISL6504, ISL6504A
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . .
Ambient Temperature
......
Range.
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. .0 to +5.5V
0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . .
65
N/A
QFN Package (Note 2) . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
VCC SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
MIN TYP MAX
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF) VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
- 17 -
-4-
Rising 5VSB POR Threshold
- - 4.5
5VSB POR Hysteresis
- 0.9 -
Rising 3V3 Threshold
- 2.75 -
3V3 Hysteresis
- 150 -
Falling Threshold Timeout (All Monitors)
- 10 -
Soft-Start Current
Shutdown Voltage Threshold
VID_PG Rising Threshold
ISS
VSD
- 10 -
- - 0.8
- 1.02 -
VID_PG Hysteresis
- 56 -
1.5VSB LINEAR REGULATOR (VOUT1)
Regulation
- - 2.0
1V5SB Nominal Voltage Level
1V5SB Undervoltage Rising Threshold
V1V5SB
- 1.5 -
- 1.25 -
1V5SB Undervoltage Hysteresis
- 75 -
1V5SB Output Current
1.2VVID LINEAR REGULATOR (VOUT2)
Regulation
I1V5SB V3V3DL = 3.3V
85 -
-
- - 2.0
1V2VID Nominal Voltage Level
1V2VID Undervoltage Rising Threshold
V1V2VID
- 1.2 -
- 0.96 -
1V2VID Undervoltage Hysteresis
- 60 -
1V2VID Output Current
I1V2VID V3V3 = 3.3V
40 -
-
UNITS
mA
mA
V
V
V
mV
µs
µA
V
V
mV
%
V
V
mV
mA
%
V
V
mV
mA
4

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ISL6504, ISL6504A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
TEST CONDITIONS
MIN TYP MAX UNITS
- - 2.0 %
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
V3V3DL
- 3.3 -
- 2.75 -
V
V
3V3DL Undervoltage Hysteresis
- 150 -
mV
3V3DLSB Output Drive Current
5VDUAL SWITCH CONTROLLER (VOUT4)
5VDL Undervoltage Rising Threshold
I3V3DLSB V5VSB = 5V
58 -
- 4.10 -
mA
V
5VDL Undervoltage Hysteresis
- 200 -
mV
5VDLSB Output Drive Current
TIMING INTERVALS
I5VDLSB V5VDLSB = 4V, V5VSB = 5V
-20 - -40 mA
Active State Assessment Past Input UV
Thresholds (Note 3)
20 25 30
ms
Active-to-Sleep Control Input Delay
- 200 -
µs
VID_CT Charging Current
CONTROL I/O (S3, S5, FAULT)
IVID_CT VVID_CT = 0V
- 10 -
µA
High Level Input Threshold
- - 2.2 V
Low Level Input Threshold
0.8 -
-
V
S3, S5 Internal Pull-up Impedance to 5VSB
- 50 -
k
FAULT Output Impedance
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
NOTES:
3. Guaranteed by Correlation.
4. Guaranteed by Design.
FAULT = high
- 100 -
125 -
- 155
-
-
oC
oC
5