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®
Data Sheet
November 2003
ISL6505
FN9109.1
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6505 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates three linear controllers/regulators, switching,
monitoring and control functions into a 20-pin wide-body
SOIC or 20-pin QFN (also known as MLF) 5x5 package.
The ISL6505’s operating mode (active or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3VDUAL/3.3VSB
voltage plane from the ATX supply’s 5VSB output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses. The
3.3VDUAL/3.3VSB output is active for as long as the ATX 5VSB
voltage is applied to the chip.
A controller powers up the 5VDUAL plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5VSB through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6505 5VDUAL output is either shut down or stays on,
based on the state of the EN5 pin.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element.
A linear controller generates VOUT1 from the
3.3VDUAL/3.3VSB voltage plane, using an external NFET.
The voltage is user-programmable to values between 1.2V
and 1.5V, using an external resistor divider. The mode is
user-selectable with the LAN pin; a logic high (or open)
selects the 10/100 LAN mode, where VOUT1 is always on
(S0-S5); a logic low selects the Gigabit Ethernet mode,
where VOUT1 is only on during active modes (S0-S2).
Ordering Information
Features
• Provides four ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
- 1.2VVID Processor VID Circuitry
- VOUT1 (1.2V - 1.5V programmable) LAN/Ethernet
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
ACPI-Compliant Power Regulation for Motherboards
Pinouts
ISL6505 (20-LEAD-WIDE SOIC) TOP VIEW
FB1 1
DR1 2
3V3DLSB 3
3V3DL 4
1V2VID 5
3V3 6
5V 7
EN5 8
S3 9
S5 10
20 5VSB
19 VID_CT
18 VID_PG
17 SS
16 LAN
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
ISL6505 (5 X 5 QFN) TOP VIEW
20 19 18 17 16
3V3DL 1
1V2VID 2
15 VID_PG
14 SS
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
DWG. #
ISL6505CB
0 to 70 20 Ld Wide SOIC M20.3
ISL6505CR
0 to 70 20 Ld 5x5 QFN L20.5x5
ISL6505EVAL1
Evaluation Board (SOIC)
ISL6505AEVAL2 Evaluation Board (QFN)
3V3 3
5V 4
EN5 5
13 LAN
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at GND potential.
It can be left unconnected, or connected to GND; do NOT connect to another potential.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
3V3DLSB
EA4
DR1
FB1
EA3 +
-
TO UV
DETECTOR
FAULT
UV DETECTOR
10µA
UV COMP
+
4.10V
-
3V3DL 5V 3V3
5VSB DLA 5VDLSB
5V MONITOR
4.5V/4.25V
5VSB POR
4.4V/3.4V
3V3 MONITOR
2.75V/2.60V
TEMPERATURE
MONITOR
(TMON)
MONITOR AND CONTROL
+
0.80V
-
TO
UV DETECTOR
+ EA3
-
TO 3V3
+
-
10mA
1V2VID
VID_PG
5VDL GND
SS
S3 S5 EN5
LAN
FIGURE 1.
VID_CT

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Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
ISL6505
FAULT
Q2
3.3VDUAL /3.3VSB
3.3V
VOUT1
Q3
Q6
R20
SHUTDOWN
SX, EN5, LAN
R21
4
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
ISL6505
LINEAR
CONTROLLER
LINEAR
REGULATOR
LINEAR
CONTROLLER
CONTROL
LOGIC
FIGURE 2.
1.2VVID
1.2V
VID_PG
Q4
Q5
5VDUAL
5V
VOUT1
1.2V - 1.5V
COUT1
Q2
RDLA
Q6
DR1
R20
FB1
R21
3V3DLSB
VOUT3
3.3VDUAL/3.3VSB
FAULT
SLP_S3
SLP_S5
SHUTDOWN
Q3
COUT3
EN5
LAN
3V3DL
EN5
LAN
FAULT
S3
S5
SS
CSS
3V3 5V 5VSB
1V2VID
VID_CT
CCT_VID
COUT2
VOUT2
1.2VVID
ISL6505
VID_PG
5VDLSB
DLA
5VDL
Q5
COUT4
VID PGOOD
Q4
VOUT4
5VDUAL
GND
FIGURE 3.
3

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ISL6505
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . .
Ambient Temperature
......
Range.
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. .0 to +5.5V
0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . .
65
N/A
QFN Package (Notes 2, 3) . . . . . . . . .
35
5
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF) VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
-6-
-4-
5VSB Rising POR Threshold
4.1 4.3 4.5
5VSB Falling POR Threshold
3.2 3.4 3.5
5VSB POR Hysteresis
- 0.9 -
3V3 Rising Threshold
2.85 2.93 3.00
3V3 Falling Threshold
2.70 2.78 2.85
3V3 Hysteresis
- 150 -
5V Rising Threshold
4.3 4.4 4.5
5V Falling Threshold
4.05 4.15 4.25
5V Hysteresis
- 250 -
VID_PG Rising Threshold
- 1.04 -
VID_PG Hysteresis
- 50 -
VID_CT Charging Current
IVID_CT
Soft-Start Current
ISS
Soft-Start Shutdown Voltage Threshold
VSD
LINEAR REGULATOR (VOUT1; DR1 and FB1 pins)
VOUT1 Regulation
VOUT1 Nominal Voltage Level
VOUT1
VOUT1 Undervoltage Rising Threshold
VOUT1 Undervoltage Hysteresis
DR1 Output Drive Current
IDR1
VVID_CT = 0V
VOUT1 = 1.2V to 1.5V
Based on external resistors
FB1 pin
FB1 pin
V3V3DL = 3.3V
- 10 -
- 10 -
- - 0.8
- - 2.0
- 1.5 -
- 1.2 -
- 50 -
- 10 -
UNITS
mA
mA
V
V
V
V
V
mV
V
V
mV
V
mV
µA
µA
V
%
V
V
mV
mA
4

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ISL6505
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
1.2VVID LINEAR REGULATOR (VOUT2)
1V2VID Regulation
- - 2.0 %
1V2VID Nominal Voltage Level
1V2VID Undervoltage Rising Threshold
V1V2VID
- 1.2 -
- 0.92 -
V
V
1V2VID Undervoltage Hysteresis
- 100 -
mV
1V2VID Output Current
I1V2VID
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
3V3DL Sleep State Regulation
V3V3 = 3.3V
- - 180 mA
- - 2.0 %
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
V3V3DL
- 3.3 -
- 2.62 -
V
V
3V3DL Undervoltage Hysteresis
- 150 -
mV
3V3DLSB Output Drive Current
5VDUAL SWITCH CONTROLLER (VOUT4)
5VDL Undervoltage Rising Threshold
I3V3DLSB V5VSB = 5V
30 50
-
mA
- 4.10 -
V
5VDL Undervoltage Hysteresis
- 120 -
mV
5VDLSB Output Drive Current
TIMING INTERVALS
I5VDLSB V5VDLSB = 4V, V5VSB = 5V
-20 - -40 mA
Active State Assessment Past Input UV
Thresholds (Note 4)
42 53 64
ms
Active-to-Sleep Control Input Delay
- 200 -
µs
Falling UV Threshold Timeout (All Monitors)
CONTROL I/O (S3, S5, EN5, LAN, FAULT)
- 10 -
µs
High Level Input Threshold
S3, S5, EN5, LAN
- - 2.2 V
Low Level Input Threshold
S3, S5, EN5, LAN
0.8 -
-
V
Internal Pull-up Current to 5VSB
S3, S5 to GND
- 50 -
µA
Internal Pull-up Current to 5VSB
EN5, LAN to GND
- 10 -
µA
Input Leakage Current to 5VSB
EN5, LAN to 5VSB
- - 10 µA
FAULT Current Ioh (to 5VSB)
FAULT = 4.6V, 5VSB = 5V
- -7.5 -
mA
FAULT Current Iol (to GND)
TEMPERATURE MONITOR
Fault-Level Threshold (Note 5)
Shutdown-Level Threshold (Note 5)
NOTES:
4. Guaranteed by Correlation.
5. Guaranteed by Design.
FAULT = 0.4V, 5VSB = 5V
- 0.75 -
125 -
- 155
-
-
mA
oC
oC
5