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®
Data Sheet
March 2003
ISL6520A
FN9016.1
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6520A makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6520A integrates
the control, output adjustment, monitoring and protection
functions into a single 8-Lead package.
The ISL6520A provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
PART NUMBER
ISL6520ACB
TEMP.
RANGE (oC)
PACKAGE
0 to 70 8 Ld SOIC
PKG.
NO.
M8.15
ISL6520AIB
ISL6520ACR
ISL6520AIR
ISL6520EVAL1
-40 to 85 8 Ld SOIC
M8.15
0 to 70 16 Ld 4x4mm QFN L16.4x4
-40 to 85 16 Ld 4x4mm QFN L16.4x4
Evaluation Board
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- SSTL-2 and DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
BOOT 1
UGATE 2
GND 3
LGATE 4
SOIC
TOP VIEW
8 PHASE
7 COMP/SD
6 FB
5 VCC
ISL6520A
QFN
TOP VIEW
16 15 14 13
BOOT 1
12 NC
UGATE 2
GND 3
GND
11 COMP/OCSET
10 NC
NC 4
9 FB
5678
Block Diagram
SAMPLE
AND
HOLD
+-
OC
COMPARATOR
VCC
POR AND
SOFTSTART
+
0.8V
-
FB
COMP/OCSET
20µA
Typical Application
ERROR
AMP
+-
PWM
COMPARATOR
+-
GATE
CONTROL
PWM LOGIC VCC
OSCILLATOR
FIXED 300kHz
VCC
GND
CDCPL
CBULK
ROCSET
RF
CF
VCC
5 BOOT
1
COMP/OCSET
ISL6520A
72
8
UGATE
PHASE
CI LGATE
63
4
FB GND
DBOOT
CHF
CBOOT
LOUT
COUT
+VO
ROFFSET
RS
2
BOOT
UGATE
PHASE
LGATE

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ISL6520A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range - ISL6520AC . . . . . . . . . . 0oC to 70oC
Ambient Temperature Range - ISL6520AI. . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . . . . 95
N/A
QFN Package (Note 2, 3). . . . . . . . . . . . . . 45
7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . -65oC to 150oC
Maximum Lead Temperature
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
Rising VCC POR Threshold
SYMBOL
IVCC
POR
TEST CONDITIONS
MIN TYP MAX UNITS
2.6 3.2 3.8
mA
4.19 4.30 4.50
V
VCC POR Threshold Hysteresis
- 0.25 -
V
OSCILLATOR
Frequency
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
ERROR AMPLIFIER
fOSC
VOSC
ISL6520AC, VCC = 5V
ISL6520AI, VCC = 5V
VREF
ISL6520AC
ISL6520AI
250 300 340
230 300 340
- 1.5 -
-1.5 - +1.5
-2.5 +2.5
- 0.800 -
kHz
kHz
VP-P
%
%
V
DC Gain
Guaranteed By Design
- 88 -
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
- 15 - MHz
- 8 - V/µs
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION / DISABLE
OCSET Current Source
Disable Threshold
IUGATE- VBOOT - VPHASE = 5V, VUGATE = 4V
SRC
IUGATE-SNK
ILGATE-SRC VVCC = 5V, VLGATE = 4V
ILGATE-SNK
IOCSET
VDISABLE
ISL6520AC
ISL6520AI
- -1 -
-1-
- -1 -
-2-
17 20 22
14 20 24
- 0.8 -
A
A
A
A
µA
µA
V
3

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ISL6520A
Functional Pin Description
VCC
This pin provides the bias supply for the ISL6520A, as well
as the lower MOSFET’s gate. Connect a well-decoupled 5V
supply to this pin.
FB
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the
converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET
This is a multiplexed pin. During a short period of time
following power-on reset (POR), this pin is used to determine
the overcurrent threshold of the converter. Connect a
resistor (ROCSET) from this pin to the drain of the upper
MOSFET (VCC). ROCSET, an internal 20µA current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the converter overcurrent (OC) trip point according to the
following equation:
IPEAK = I--O-----C----S---r-E-D---T-S---x-(--RO-----ON----)C----S----E----T--
Internal circuitry of the ISL6520A will not recognize a voltage
drop across ROCSET larger than 0.5V. Any voltage drop
across ROCSET that is greater than 0.5V will set the
overcurrent trip point to:
IPEAK = r---D---0-S--.--5(--O-V---N-----)
An overcurrent trip cycles the soft-start function.
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error
amplifier. Use this pin, in combination with the
COMP/OCSET pin, to compensate the voltage-control
feedback loop of the converter.
Pulling COMP/OCSET to a level below 0.8V disables the
controller. Disabling the ISL6520A causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
Functional Description
Initialization
The ISL6520A automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Overcurrent Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
Over Current Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, rDS(ON),
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level (see Typical Application
diagram).
Immediately following POR, the ISL6520A initiates the
Overcurrent Protection sampling and hold operation. First,
the internal error amplifier is disabled. This allows an internal
20µA current sink to develop a voltage across ROCSET. The
ISL6520A then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Overcurrent Set Point.
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Overcurrent Set
Point, the overcurrent function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6520A to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
Start interval and causes an overcurrent trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
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OUTPUT INDUCTOR
CURRENT
5A/DIV.
ISL6520A
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
COMP/OCSET
1V/DIV.
VOUT
500mV/DIV.
TIME (5ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
IPEAK = I--O-----C----S----E-r--D-T---S--x--(--O-R----N-O---)-C-----S----E---T--
where IOCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid overcurrent tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2.
3.
The minimum IOCSET
Determine IPEAK for
where I is the output
from the specification table.
IPEAK
>
IOUT(MAX)
+
(-------I---)
2
,
inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
Soft Start
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (non-
inverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the overcurrent setpoint by disabling the error
amplifier and drawing 20µA through ROCSET. Once the
overcurrent level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
TIME (2ms/DIV.)
FIGURE 2. SOFT START INTERVAL
Current Sinking
The ISL6520A incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6520A when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the VCC
rail, which supplies the bias voltage to the ISL6520A. If there
is nowhere for this current to go, such as to other distributed
loads on the VCC rail, through a voltage limiting protection
device, or other methods, the capacitance on the VCC bus
will absorb the current. This situation will allow voltage level
of the VCC rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520A, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
5