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®
Data Sheet
April 2003
ISL6520B
FN9083.1
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6520B makes simple work out of implementing a
complete control scheme for a DC-DC stepdown converter.
Designed to drive N-channel MOSFETs in a synchronous
buck topology, the ISL6520B integrates the control, output
adjustment and monitoring functions into a single 8-Lead
package.
The ISL6520B provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
ISL6520BCB
0 to 70 8 Ld SOIC
M8.15
ISL6520BIB
-40 to 85 8 Ld SOIC
M8.15
ISL6520BCR
0 to 70 16 Ld 4x4mm QFN L16.4x4
ISL6520BIR
-40 to 85 16 Ld 4x4mm QFN L16.4x4
ISL6520EVAL1 Evaluation Board
Pinouts
ISL6520B (8 LD SOIC)
TOP VIEW
BOOT 1
UGATE 2
GND 3
LGATE 4
8 PHASE
7 COMP/SD
6 FB
5 VCC
ISL6520B (16 LD QFN)
TOP VIEW
16 15 14 13
BOOT 1
12 NC
UGATE 2
GND 3
GND
11 COMP/SD
10 NC
NC 4
9 FB
5678
Features
• Operates from +5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- SSTL-2 and DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 5V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
+
0.8V
-
FB
COMP/SD
20µA
Typical Application
ISL6520B
VCC
POR AND
SOFTSTART
ERROR
AMP
+-
PWM
COMPARATOR
+-
GATE
CONTROL
PWM LOGIC VCC
OSCILLATOR
FIXED 300kHz
GND
BOOT
UGATE
PHASE
LGATE
SHUTDOWN
5V
RPULLUP
RF
CF
ROFFSET
CDCPL
DBOOT
COMP/SD
VCC
5
1
ISL6520B
72
8
BOOT
CBOOT
UGATE
PHASE
CI LGATE
63
4
FB GND
VIN
CHF
CBULK
QU
LOUT
QL COUT
VOUT
RS
2

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ISL6520B
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range - ISL6520BC . . . . . . . . . . 0oC to 70oC
Ambient Temperature Range - ISL6520BI . . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . . . . 95
N/A
QFN Package (Note 2, 3). . . . . . . . . . . . . . 45
7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . -65oC to 150oC
Maximum Lead Temperature
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
IVCC
2.6 3.2 3.8
mA
Rising VCC POR Threshold
POR
4.19 4.30 4.50
V
VCC POR Threshold Hysteresis
- 0.25 -
V
OSCILLATOR
Frequency
fOSC
ISL6520BC, VCC = 5V
ISL6520BI, VCC = 5V
250 300 340
230 300 340
kHz
kHz
Ramp Amplitude
REFERENCE
VOSC
- 1.5 - VP-P
Reference Voltage Tolerance
ISL6520BC
-1.5 - +1.5 %
ISL6520BI
-2.5 +2.5 %
Nominal Reference Voltage
ERROR AMPLIFIER
VREF
- 0.800 -
V
DC Gain
Guaranteed By Design
- 88 -
dB
Gain-Bandwidth Product
GBWP
- 15 - MHz
Slew Rate
SR
- 8 - V/µs
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
DISABLE
IUGATE-
SRC
VBOOT - VPHASE = 5V, VUGATE = 4V
IUGATE-SNK
ILGATE-SRC VVCC = 5V, VLGATE = 4V
ILGATE-SNK
- -1 -
-1-
- -1 -
-2-
A
A
A
A
Disable Threshold
VDISABLE
- 0.8 -
V
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ISL6520B
Functional Pin Description
VCC
This pin provides the bias supply for the ISL6520B, as well
as the lower MOSFET’s gate. Connect a well-decoupled 5V
supply to this pin.
FB
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/SD pin, to
compensate the voltage-control feedback loop of the
converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/SD
This pin is the output of the error amplifier. Use this pin, in
combination with the FB pin, to compensate the voltage-
control feedback loop of the converter.
Pulling COMP/SD to a level below 0.8V disables the
controller. Disabling the ISL6520B causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm. The COMP/SD pin must be
pulled above 0.8V to terminate shutdown. This may be done
through a pullup resistor tied between VCC and COMP/SD.
The recommended range of resistor values to use as the pullup
resistor is between 50kand 100k.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
Functional Description
Initialization
The ISL6520B automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the soft
start operation.
Soft Start
The ISL6520B is held in reset with both UGATE and LGATE
driven to ground until the POR threshold on VCC has been
reached and the COMP/SD pin has been pulled above 0.8V. If
COMP is not actively pulled high following POR the internal
20µA current sink will hold COMP/SD low and the device will
remain in reset. COMP/SD can either be statically tied to VCC
through a pullup resistor or driven high through a resistor to
terminate reset. The recommended range of resistor values to
use as the pullup resistor is between 50kand 100k.
Following reset the ISL6520B provides a 1024 clock cycle
settling period (~3.4ms) prior to initiating softstart. At the
conclusion of the settling period the COMP/SD pin is driven
to 0.8V for 24 clock cycles (~75µs) to discharge the
compensation network. Soft start of the regulated output is
generated by imposing an internal offset on the FB pin which
ramps down from 0.8V to 0V over the next 2048 clock cycles
(~6.8ms). Total time from end of reset to completion of soft start
is 10.2ms.
Pulling COMP/SD below.8V or VCC dropping below
minimum POR initiates another reset.
VCOMP/SD
1V/DIV.
VOUT
500mV/DIV.
TIME (2ms/DIV.)
FIGURE 1. SOFT START INTERVAL
Current Sinking
The ISL6520B incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6520B when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the VCC
4

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ISL6520B
rail, which supplies the bias voltage to the ISL6520B. If there
is nowhere for this current to go, such as to other distributed
loads on the VCC rail, through a voltage limiting protection
device, or other methods, the capacitance on the VCC bus
will absorb the current. This situation will allow voltage level
of the VCC rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520B, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
ISL6520B
VIN
UGATE
PHASE
LGATE
Q1
Q2
LO VOUT
CIN
CO
RETURN
FIGURE 2. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 2 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 2 should be located as close together as possible.
Please note that the capacitors CIN and CO may each
represent numerous physical capacitors. Locate the ISL6520B
within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520B must be sized to handle up to 1A peak current.
Figure 3 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/SD pin and locate the resistor,
ROSCET close to the COMP/SD pin because the internal
current source is only 20µA. Provide local VCC decoupling
between VCC and GND pins. Locate the capacitor, CBOOT
as close as practical to the BOOT and PHASE pins. All
components used for feedback compensation should be
located as close to the IC a practical.
ISL6520B
BOOT
CBOOT
D1
PHASE
VCC +5V
+VIN
Q1 LO
Q2 CO
VOUT
GND
CVCC
FIGURE 3. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
VIN at the PHASE node. The PWM wave is smoothed by the
output filter (LO and CO).
VOSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VOUT
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB VOUT
ZIN
C3 R3
COMP/SD
- FB
+
ISL6520B
REFERENCE
R1
FIGURE 4. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
5