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TM
Data Sheet
ISL6525
March 2001 File Number 4998.1
Buck and Synchronous-Rectifier
Pulse-Width Modulator (PWM) Controller
The ISL6525 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N Channel MOSFETs in a synchronous-rectified buck
topology. The ISL6525 integrates all of the control, output
adjustment, monitoring and protection functions into a single
package. A programmable delay time for the PGOOD signal
makes it especially suitable for the VTT regulation in
VRM8.5 applications.
The output voltage of the converter can be precisely
regulated to as low as 1.20V, with a maximum tolerance of
±1% over temperature and line voltage variations.
The ISL6525 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The ISL6525 protects against over-current conditions by
inhibiting PWM operation. The ISL6525 monitors the current
by using the rDS(ON) of the upper MOSFET which eliminates
the need for a current sensing resistor.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ISL6525CB
0 to 70 14 Ld SOIC
PKG.
NO.
M14.15
Features
• Drives Two N-Channel MOSFETs
• Operates From +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- 1.20V Internal Reference
- ±1% Over Line Voltage and Temperature
• Programmable delay for PGOOD signal
• Over-Current Fault Monitor
- Does Not Require Extra Current Sensing Element
- Uses MOSFETs rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to Over 1MHz
• 14 Pin, SOIC Package
Applications
• Power Supply for Various Microprocessors
• VTT Regulation for VRM8.5
• High-Power 5V to 3.xV DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
ISL6525
(SOIC)
TOP VIEW
RT 1
OCSET 2
SS 3
COMP 4
FB 5
GND 6
PGOOD 7
14 DELAY
13 VCC
12 LGATE
11 PGND
10 BOOT
9 UGATE
8 PHASE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved

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ISL6525
Typical Application
SS
12V
VCC
MONITOR AND
PROTECTION
RT
OSC
ISL6525
REF
-
FB
++
-
COMP
OCSET
BOOT
UGATE
PHASE
PVCC +12V
LGATE
PGND
GND
+5V OR +12V
+VO
Block Diagram
OCSET
FB
COMP
RT
VCC
REFERENCE
110%
+
-
POWER-ON
RESET (POR)
90%
+
-
VCC 10µA
10µA
200µA
+- OVER-
CURRENT
4V
SOFT-
START
DACOUT
+
-
ERROR
AMP
PWM
COMPARATOR
+
-
INHIBIT
PWM
GATE
CONTROL
LOGIC
OSCILLATOR
DELAY
PGOOD
SS
BOOT
UGATE
PHASE
LGATE
PGND
GND
2

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ISL6525
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Boot Voltage, VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . .
Ambient Temperature Range
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+12V ±10%
0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
117
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead tips only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
ICC EN = VCC; UGATE and LGATE Open
EN = 0V
- 5 - mA
-
50 100
µA
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
Enable - Input threshold Voltage
Rising VOCSET Threshold
OSCILLATOR
VOCSET = 4.5VDC
VOCSET = 4.5VDC
VOCSET = 4.5VDC
- - 10.4
8.2 -
-
0.8 - 2.0
- 1.27 -
V
V
V
V
Free Running Frequency
Total Variation
Ramp Amplitude
REFERENCE
VOSC
RT = OPEN, VCC = 12
6k< RT to GND < 200k
RT = OPEN
185 200 215
kHz
-15 - +15 %
- 1.9 - VP-P
Reference Voltage
1.188 1.20 1.212
V
ERROR AMPLIFIER
DC Gain
- 88 -
dB
Gain-Bandwidth Product
GBW
- 15 - MHz
Slew Rate
SR COMP = 10pF
- 6 - V/µs
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
PROTECTION
IUGATE
RUGATE
ILGATE
RLGATE
VBOOT - VPHASE = 12V, VUGATE = 6V
ILGATE = 0.3A
VCC = 12V, VLGATE = 6V
ILGATE = 0.3A
350 500
-
- 5.5 10
300 450
-
- 3.5 6.5
mA
W
mA
W
OCSET Current Source
Soft Start Current
PGOOD DELAY
IOCSET
ISS
VOCSET = 4.5VDC
170 200 230
- 10 -
µA
µA
Discharge Current Source
5.5 10 14.5 µA
NMOS gate threshold voltage
-2-
V
3

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ISL6525
Typical Performance Curves
1000
100
10
RT PULLUP
TO +12V
RT PULLDOWN
TO VSS
10 100
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
1000
Functional Pin Descriptions
RT (Pin 1)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Fs 200kHz + R--5---T----(--1k---0----6--)
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation.:
Fs 200kHz – -R-4---T----(--1k---0----7--)
(RT to 12V)
OCSET (Pin 2)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 200µA current source
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set
the converter over-current (OC) trip point according to the
following equation:
IPEAK = I--O-----C----Sr--D-----S--R-(---O-O---N-C---)--S----E---T--
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
COMP (Pin 4) and FB (Pin 5)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
80
70
60
CGATE = 3300pF
50
40
30 CGATE = 1000pF
20
10 CGATE = 10pF
0
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
GND (Pin 6)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
PGOOD (Pin 7)
PGOOD is an open-drain output used to indicate the status
of the converter output voltage. This pin is pulled low when
the converter output is not within ±10% of the set voltage. A
delay time can be programmed using the DELAY pin (pin
14). See Pin 14 description for more information.
PHASE (Pin 8)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
UGATE (Pin 9)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 10)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND (Pin 11)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 12)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 13)
Provide a 12V bias supply for the chip to this pin.
DELAY (Pin 14)
This pin is used to program the delay of the PGOOD (pin 7)
signal by placing a capacitor between this pin and GND or
VCC. The external capacitor only delays the rising edge of
4

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ISL6525
PGOOD signal, not the falling edge. An internal hysteresis
guarantees glitch-free transition of PGOOD. Refer to
Programming PGOOD Delay Time section for more
information.
Functional Description
Initialization
The ISL6525 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (VIN) on the OCSET pin. The level on
OCSET is equal to VIN less a fixed voltage drop (see over-
current protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, VIN
and VCC are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft start sequence. An internal
10µA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to
the SS pin voltage. Figure 3 shows the soft start interval with
CSS = 0.1µF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t1 in Figure 3,
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE
pulses of increasing width that charge the output capacitor(s).
This interval of increasing pulse width continues to t2. With
sufficient output voltage, the clamp on the reference input
controls the output voltage. This is the interval between t2 and
t3 in Figure 3. At t3 the SS voltage exceeds the reference
voltage and the output voltage is in regulation. This method
provides a rapid and controlled output voltage rise.
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
rDS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the over-current trip level. An internal 200µA (typical)
current sink develops a voltage across ROCSET that is
reference to VIN. When the voltage across the upper MOSFET
(also referenced to VIN) exceeds the voltage across ROCSET,
the over-current function initiates a soft-start sequence. The
soft-start function discharges CSS with a 10µA current sink and
inhibits PWM operation. The soft-start function recharges CSS,
and PWM operation resumes with the error amplifier clamped
to the SS voltage. Should an overload occur while recharging
CSS, the soft start function inhibits PWM operation while fully
charging CSS to 4V to complete its cycle. Figure 4 shows this
operation with an overload condition. Note that, in this particular
application, the inductor current increases to over 15A during
the CSS charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured average input power for the conditions of Figure 4 is
2.5W.
4V
2V
0V
15A
10A
5A
0A
SOFT-START
(1V/DIV.)
OUTPUT
VOLTAGE
0V (1V/DIV.)
0V
t1 t2
t3
TIME (5ms/DIV.)
FIGURE 3. SOFT-START INTERVAL
TIME (20ms/DIV.)
FIGURE 4. OVER-CURRENT OPERATION
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
IPEAK = I--O-----C----S----rE--D--T--S----(--O-R----NO----)-C----S----E----T--
where IOCSET is the internal OCSET current source (200µA
- typical). The OC trip point varies mainly due to the
MOSFETs rDS(ON) variations. To avoid over-current tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
5