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®
Data Sheet
July 2003
ISL6531
FN9053.1
Dual 5V Synchronous Buck Pulse-Width
Modulator (PWM) Controller for DDRAM
Memory VDDQ and VTT Termination
The ISL6531 provides complete control and protection for
dual DC-DC converters optimized for high-performance
DDRAM memory applications. It is designed to drive low
cost N-channel MOSFETs in synchronous-rectified buck
topology to efficiently generate 2.5V VDDQ for powering
DDRAM memory, VREF for DDRAM differential signalling,
and VTT for signal termination. The ISL6531 integrates all of
the control, output adjustment, monitoring and protection
functions into a single package.
The VDDQ output of the converter is maintained at 2.5V
through an integrated precision voltage reference. The VREF
output is precisely regulated to 1/2 the memory power
supply, with a maximum tolerance of ±1% over temperature
and line voltage variations. VTT accurately tracks VREF.
During V2_SD sleep mode, the VTT output is maintained by
a low power window regulator.
The ISL6531 provides simple, single feedback loop, voltage-
mode control with fast transient response for the VDDQ
regulator. The VTT regulator features internal compensation
that eases the design. It includes two phase-locked 300kHz
triangle-wave oscillators which are displaced 90o to
minimize interference between the two PWM regulators. The
regulators feature error amplifiers with a 15MHz gain-
bandwidth product and 6V/µs slew rate which enables high
converter bandwidth for fast transient performance. The
resulting PWM duty ratio ranges from 0% to 100%.
The ISL6531 protects against overcurrent conditions by
inhibiting PWM operation. The ISL6531 monitors the current
in the VDDQ regulator by using the rDS(ON) of the upper
MOSFET which eliminates the need for a current sensing
resistor.
Ordering Information
TEMP
PART NUMBER RANGE(oC) PACKAGE PKG. DWG. #
ISL6531CB
0 to 70 24 Lead SOIC M24.3
ISL6531CR
0 to 70 32 Lead 5x5 QFN L32.5x5
ISL6530/31EVAL1 Evaluation Board
Features
• Provides VDDQ, VREF, and VTT voltages for one- and
two- channel DDRAM memory systems
• Excellent voltage regulation
- VDDQ = 2.5V ±2% over full operating range
-
VREF =
1--
2
VDDQ
±1%
over
full
operating
range
- VTT = VREF ± 30mV
• Supports ‘S3’ sleep mode
-
VTT is held
regulator to
amt in12--imVizDeDwQakveia-uaplotiwmepower
window
• Fast transient response
- Full 0% to 100% duty ratio
• Operates from +5V Input
• VTT regulator internally compensated
• Overcurrent fault monitor on VDD
- Does not require extra current sensing element
- Uses MOSFET’s rDS(ON)
• Drives inexpensive N-Channel MOSFETs
• Small converter size
- 300kHz fixed frequency oscillator
• 24 Lead, SOIC or 32 Lead, 5mm×5mm QFN
Applications
• VDDQ, VTT, and VREF regulation for DDRAM memory
systems
- Main memory in AMD® Athlon™ and K8™, Pentium®
III, Pentium IV, Transmeta, PowerPC™, AlphaPC™,
and UltraSparc® based computer systems
• High-power tracking DC-DC regulators
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

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Pinouts
24 LEAD (SOIC)
TOP VIEW
UGATE1 1
BOOT1 2
PHASE1 3
VREF 4
FB1 5
COMP1 6
SENSE1 7
VREF_IN 8
GNDA 9
PHASE2 10
BOOT2 11
UGATE2 12
24 PGND1
23 LGATE1
22 PVCC1
21 OCSET/SD
20 V2_SD
19 PGOOD
18 N/C
17 SENSE2
16 N/C
15 VCC
14 LGATE2
13 PGND2
ISL6531
32 LEAD 5X5 (QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PHASE 1 1
24 PVCC1
VREF 2
23 OCSET/SD
FB1 3
22 V2_SD
COMP1 4
21 PGOOD
SENSE1 5
20 N/C
VREF_IN 6
19 SENSE2
GNDA 7
18 N/C
GNDA 8
17 VCC
9 10 11 12 13 14 15 16
2

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Block Diagram
PGOOD
FB1
COMP1
SENSE1
VREF_IN
VREF
+
-
SENSE2
V2_SD
ISL6531
OCSET/SD
VCC
POWER-ON
RESET (POR)
40µA
+
-
OVER-
CURRENT
SOFT-
START
ERROR
AMP
+
-
PWM
COMPARATOR
+
-
INHIBIT
PWM
GATE
CONTROL
LOGIC
0.8V
REFERENCE
OSCILLATOR
ERROR
AMP
+
Zf -
Zc
WINDOW
REGULATOR
90o Phase
Shift
- PWM
+
PWM
INHIBIT
COMPARATOR
GATE
CONTROL
LOGIC
VCC
GND
BOOT1
UGATE1
PHASE1
PVCC1
LGATE1
PGND1
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
3

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Typical Application
+5V
ISL6531
PGOOD
RESET
ROCSET
VCC
OCSET/SD
GNDA
PGOOD
BOOT1
UGATE1
PHASE1
SLEEP
VREF
(.5xVDDQ)
RFB1
V2_SD
ISL6531
VREF_IN
VREF
COMP1
PVCC1
LGATE1
PGND1
BOOT2
UGATE2
PHASE2
FB1
SENSE1
LGATE2
SENSE2
PGND2
DBOOT1
CBOOT1
+5V
Q1
LOUT1
Q2
DBOOT2
CBOOT2
Q3
LOUT2
Q4
VDDQ
COUT1
VTT
COUT2
FIGURE 1. TYPICAL APPLICATION FOR ISL6531
4

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ISL6531
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Boot Voltage, VBOOTn - VPHASEn. . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Note 1) . . . . . . . . . . . .
65
N/A
QFN Package (Note 2). . . . . . . . . . . . .
33
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead tips only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions with Vcc = 5V, unless otherwise noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
VCC SUPPLY CURRENT
Nominal Supply
ICC OCSET/SD=VCC; UGATE1, UGATE2,
LGATE1, and LGATE2 Open
-5
Shutdown Supply
OCSET/SD=0V
-3
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
OSCILLATOR
VOCSET/SD=4.5V
VOCSET/SD=4.5V
4.25 -
3.75 -
Free Running Frequency
REFERENCES
VCC=5
275 300
Reference Voltage
(V2 Error Amp Reference)
VVREF SENSE1=2.5V
49.5 50.0
V1 Error Amp Reference Voltage
Tolerance
--
V1 Error Amp Reference
ERROR AMPLIFIERS
VREF VCC=5
- 0.8
DC Gain
- 82
Gain-Bandwidth Product
GBW
- 15
Slew Rate
SR COMP=10pF
-6
WINDOW REGULATOR
Load Current
- ±10
Output Voltage Error
V2_SD=VCC; ±10mA load on V2
- ±7
GATE DRIVERS
Upper Gate Source (UGATE1 and 2)
Upper Gate Sink (UGATE1 and 2)
Lower Gate Source (LGATE1 and 2)
Lower Gate Sink (LGATE1 and 2)
PROTECTION
IUGATE
IUGATE
ILGATE
ILGATE
VCC=5V, VUGATE=2.5V
VUGATE-PHASE=2.5V
VCC=5V, VLGATE=2.5V
VLGATE=2.5V
- -1
-1
- -1
-2
OCSET/SD Current Source
OCSET/SD Disable Voltage
IOCSET
VRESET
VOCSET=4.5VDC
34 40
- 0.8
MAX UNITS
- mA
- mA
4.5 V
4.0 V
325 kHz
50.5 %SENSE1
2%
-V
- dB
- MHz
- V/µs
- mA
-%
-A
-A
-A
-A
46 µA
-V
5