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®
Data Sheet
December 2003
ISL6532
FN9112.2
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
reference is provided as VREF.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of ±2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation in
a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD signal
indicates that all supplies are within spec and operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the VTT and VDDQ standby
regulators. Thermal shutdown is integrated.
Pinout
ISL6532 (QFN) TOP VIEW
20 19 18 17 16
5VSBY 1
GND 2
VTT 3
VTT 4
VDDQ 5
GND
21
15 NCH
14 PGOOD
13 GND
12 COMP
11 FB
6 7 8 9 10
Features
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection and Under/Over-Voltage
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
ISL6532CR
0 to 70 20 Ld 6x6 QFN
PKG.
DWG. #
L20.6x6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
P3V3SBY
VDDQ S3
REGULATOR
VDDQ(2)
VTTSNS
VTT(2)
VTT
REG
DISABLE
{
RU
VREF_IN
{
RL
SLP_S3# SLP_S5#
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
0.920V (+15%)
5VSBY
5V
POR
S3
S0
S0/S3
SLEEP,
SOFT-START,
PGOOD,
AND FAULT
LOGIC
PWM ENABLE
SOFT-START
EA1
OSCILLATOR
250kHz
PWM
COMP
UV/OV
VREF_OUT
UV/OV
PGOOD
FB COMP
NCH
PWM
LOGIC
12V
POR
P12V
UGATE
LGATE
GND

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ISL6532
Simplified Power System Diagram
5VSBY
12V
SLP_S3
SLP_S5
5VSBY/3V3SBY
SLEEP
STATE
LOGIC
PWM
CONTROLLER
ISL6532
STANDBY
LDO
VTT
REGULATOR
5V
Q1
VDDQ
+
Q2
VREF
VTT
+
Typical Application - 5V or 3.3V Input
+3.3V CBP
5VSBY
+12V
VREF
PGOOD
VDDQ
SLP_S3
S3#
SLP_S5
S5#
VREF_OUT
VREF_IN
+
CSS
VTT
+
CVTT
VTT
VTT
VTTSNS
ISL6532
NCH
UGATE
LGATE
VDDQ
VDDQ
FB
COMP
+5V OR +3.3V
RNCH
+
CIN
Q1
LOUT
Q2
VDDQ
2.5V
+
CVDDQ
GND
3

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ISL6532
Typical Application - Input From 5V Dual
+3.3V CBP
5VSBY
+12V
VREF
PGOOD
VDDQ
SLP_S3
S3#
SLP_S5
S5#
VREF_OUT
VREF_IN
CSS
VTT
+
CVTT
VTT
VTT
VTTSNS
ISL6532
NCH
UGATE
LGATE
VDDQ
VDDQ
FB
COMP
5V DUAL
RNCH
+
CIN
Q1
LOUT
Q2
VDDQ
2.5V
+
CVDDQ
GND
4

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ISL6532
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSBY + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (oC/W) θJC (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Supply Voltage on 3V3SBY . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
ICC_S0
ICC_S3
S3# & S5# HIGH, UGATE/LGATE Open
S3# LOW, S5# HIGH, UGATE/LGATE
Open
3.00 5.25 7.25
3.50 - 4.75
mA
mA
ICC_S5
S5# LOW, S3# Don’t Care,
UGATE/LGATE Open
300 - 800
µA
POWER-ON RESET
Rising 5VSBY POR Threshold
4.00 - 4.35
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Error Amp Reset Time
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
fOSC
VOSC
tRESET
tSS
S5# LOW to S5# HIGH
S5# LOW to S5# HIGH
220 250 280
- 1.5 -
6.5 - 9.5
6.5 - 9.5
kHz
V
ms
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
STATE LOGIC
S3# Transition Level
S5# Transition Level
VS3
VS5
- 1.5 -
- 1.5 -
V
V
5