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®
Data Sheet
December 2003
ISL6532A
FN9099.2
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
S0/S1 state, a fully integrated sink-source regulator
generates an accurate (VDDQ/2) high current VTT voltage
without the need for a negative supply. A buffered version of
the VDDQ/2 reference is provided as VREF. An LDO
controller is also integrated for AGP core voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and standby LDO provide a maximum static
regulation tolerance of ±2% over line, load, and temperature
ranges. The output is user-adjustable by means of external
resistors down to 0.8V.
Switching memory core output between the PWM regulator
and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the PGOOD signal
indicates VTT is within spec and operational.
Each output is monitored for under and over-voltage events.
The switching regulator has over current protection. Thermal
shutdown is integrated.
Pinout
ISL6532A (QFN) TOP VIEW
28 27 26 25 24 23 22
GNDP 1
21 PGOOD
5VSBY 2
20 PHASE
GNDQ 3
GNDQ 4
VTT 5
GND
29
19 DRIVE2
18 FB2
17 GNDA
VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 3 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
- LDO Regulator for 1.5V Video and Core voltage
• ACPI compliant sleep state control
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
ISL6532ACR
0 to 70
28 Ld 6x6 QFN
PKG.
NO.
L28.6x6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
VDDQ(3)
P5VSBY
VDDQ S3
REGULATOR
+
-
VTTSNS
VTT(2)
VTT
- REG
+
GNDQ
DISABLE
{
RU
VREF_IN
{
RL
GNDA
+-
VREF_OUT
+
-
UV/OV2
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
0.920V (+15%)
S3#
S5#
5VSBY
5V
POR
S3
S0
S0/S3
SLEEP,
SOFT-START,
PGOOD,
AND FAULT
LOGIC
UV/OV
PWM ENABLE
-
+
UV/OV3
SOFT-START
+
-
EA1
+
-
COMP
PWM
OSCILLATOR
250kHz
12VCC
+ EA2
- 650OUTPUT
IMPEDANCE
PWM
LOGIC
12V
POR
- UV/OV1
+
+
-
OC
COMP
20µA
PGOOD
FB COMP
OCSET
GNDP
DRIVE2
FB2
NCH
P12V
UGATE
PHASE
LGATE

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ISL6532A
Simplified Power System Diagram
5VSBY
12V
ISL6532A
SLP_S3
SLP_S5
SLEEP
STATE
LOGIC
PWM
CONTROLLER
5VSBY/3V3SBY
VDDQ
VAGP
+
Q3
LINEAR
CONTROLLER
STANDBY
LDO
VTT
REGULATOR
5V
NCH
Q1
Q2
VDDQ
+
VREF
VTT
+
Typical Application - 5V or 3.3V Input
+3.3V
CBP
5VSBY
+12V
+5V or +3.3V
PGOOD
VDDQ
VREF
SLP_S3
SLP_S5
S3#
S5#
VREF_OUT
VREF_IN
+
VTT
VDDQ
Q3
VTT
VTT
+
CVTT_OUT
VTTSNS
DRIVE2
VAGP
1.5V
+
COUT2
FB2
ISL6532A
NCH
RNCH
OCSET
UGATE
PHASE
ROCSET
LGATE
VDDQ
VDDQ
VDDQ
GNDQ
GNDQ
FB
COMP
GNDP
GNDA
Q4
+
CIN
Q1
LOUT
Q2
VDDQ
2.5V
+
CVDDQ_OUT
3

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ISL6532A
Typical Application - Input From 5V Dual
+3.3V
CBP
5VSBY
+12V
5V Dual
PGOOD
VDDQ
VREF
SLP_S3
SLP_S5
S3#
S5#
VREF_OUT
VREF_IN
VTT
VDDQ
Q3
VAGP
1.5V
+
COUT2
VTT
VTT
+
CVTT_OUT
VTTSNS
DRIVE2
FB2
ISL6532A
NCH
OCSET
UGATE
PHASE
ROCSET
LGATE
VDDQ
VDDQ
VDDQ
GNDQ
GNDQ
FB
COMP
GNDP GNDA
+
CIN
Q1
LOUT
Q2
VDDQ
2.5V
+
CVDDQ_OUT
4

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ISL6532A
Absolute Maximum Ratings
5VSBY, P5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LEVEL 1
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Supply Voltage onP5VSBY . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (oC/W) θJC (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
ICC_S0
ICC_S3
S3# & S5# HIGH, UGATE/LGATE Open
S3# LOW, S5# HIGH, UGATE/LGATE
Open
3.00 5.25 7.25
3.50 - 4.75
mA
mA
ICC_S5
S5# LOW, S3# Dont’t Care,
UGATE/LGATE Open
300 - 800
µA
POWER-ON RESET
Rising 5VSBY POR Threshold
4.00 - 4.35
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Error Amp Reset Time
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
fOSC
VOSC
tRESET
tSS
Mechanical Off/S5 to S0
Mechanical Off/S5 to S0
220 250 280
- 1.5 -
6.5 - 9.5
6.5 - 9.5
kHz
V
ms
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
STATE LOGIC
S3# Transition Level
S5# Transition Level
VS3
VS5
- 1.5 -
- 1.5 -
V
V
5