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®
Data Sheet
January 2004
ISL6536A
FN9136
Four Channel Supervisory IC
The ISL6536A is a four channel supervisory IC designed to
monitor voltages >, = 0.7V. This IC bias range is from 2.7V
to 5V but can supervise any positive voltage using an
external resistor divider to translate to a lower voltage for
comparison to the internal 0.63V reference.
Once properly biased and enabled when all four voltage
monitor (VMON) inputs are satisfied the PGOOD output will
be immediately released to go high to signal that voltage is
valid on all four rails. Subsequently when the monitored
voltage on any rail drops below its user defined threshold
point, the PGOOD output is pulled low. Each rail’s VMON
point is independently adjustable with a resistor divider. The
PGOOD output is guaranteed to be valid with IC bias lower
than 1V. The VMON inputs will ignore 30µs transients on the
monitored supplies. The PGOOD output is an open-drain to
allow ORing of multiple signals and interfacing to a range of
logic levels. The ENABLE input provides for a reset of the
PGOOD output when it is pulled down below 0.5V. With an
internal 10uA pull-up to VDD it can be signalled with
common logic or pulled to ground with a push button switch.
Typical Application Schematic
*OPT
ISL6536A
1 VDD
2 PGD
3 EN
4 GND
VMON1 8
VMON2 7
VMON3 6
VMON4 5
Features
• 1% VMON Threshold accuracy
• Adjustable undervoltage lockout for each supply
• Active high PGOOD Output
• Guaranteed PGOOD Valid to Falling VDD < 1V
• VMON Glitch Immunity
Applications
• Graphics Cards
• Multi voltage DSPs and Processors
• µP Voltage Monitoring
• Embedded Control Systems
• Intelligent Instruments
• Medical Equipment
• Network Routers
• Portable Battery-Powered Equipment
• Set-Top Boxes
• Telecommunications Systems
Ordering Information
PART
NUMBER
ISL6536AIB
TEMP. RANGE
(oC)
PACKAGE
PKG.
DWG. #
-40 to +85 8 Lead SOIC M8.15
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

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ISL6536A
Pin Descriptions
ISL6536A
1
2
PIN NAME
VDD
PGOOD
3 ENABLE
4 GND
5-8 VMON1
VMON2
VMON3
VMON4
FUNCTION DESCRIPTION
Bias IC from nominal 2.7V to 5V
PGOOD is the boolean AND function of all the UV inputs being satisfied. This is an open drain output and
can be pulled high to the appropriate level with an external resistor. Additionally a 20kpull up to VDD is
provided internally.
Enabling input for supervisory function. Has a 10µA pull-up to VDD
IC ground
These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.633V
reference with 1% accuracy. These inputs have a 30µs glitch filter to prevent transient upsets from being
recognized by PGOOD.
VDD
EN
VMON1
VMON2
VMON3
VMON4
10µA
20K
FALLING EDGE
GLITCH FILTER
PGOOD
+
633mV
-
ISL6536A
2

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ISL6536A
Absolute Maximum Ratings
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM)
Operating Conditions
VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
2. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications Nominal VDD = 3.3V, TA = TJ = -40oC - 85oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
BIAS
IC Supply Current
VDD Power On
IVDD
VDD_L2H
VMON > VMON_L2H
VDD low to high
- 165 1000 µA
- 2.6 - V
VDD Power On Reset
VDD_POR VDD high to low
- 2.4 - V
PGOOD
Pull-Down Current
Pull-Up Resistance
Output Low
Delay from VMON Rising
Delay from EN Rising
Delay from EN Falling
ENABLE
PGpd
PGpu
VPGl
TPGdelVMON
TPGdelENR
TPGdelENF
VPGOOD = 0.5V
VDD= 1V
Last valid input = Vth to PG release
EN high to PG release
EN low to PG pulling low
- 2 - mA
- 20 - k
-
0.05 0.1
V
- 2 - µs
- 0.05 - µs
- 0.015 -
µs
Rising Threshold
Threshold Hysteresis
Pull-up Current
VMON INPUT
VEN
VEN_HYS
IENpu
ENABLE Low to High Threshold
VEN = 0.5V
0.4VDD 0.5VDD 0.6VDD
- 0.065 -
- 10 -
V
V
µA
Falling Threshold
Falling Threshold Temp Coefficient
Hysteresis
Range
Glitch Filter Duration
3.3VMON_H2L
3.3VMON_TC
VVMON_HYS
VMON_RNG
TFIL
Tj=+25c
VMON glitch to PGOOD low Filter
0.627
-
-
-
-
0.633
33
10
1
30
0.639
-
-
-
-
V
µV/oC
mV
mV
µs
3

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ISL6536A
ISL6536A Description and Operation
The ISL6536A is a four channel supervisory IC with industry
leading 1% tolerance and 1mV range between channels.
This IC is designed to monitor multiple voltages greater than
0.7V and is suitable for both microprocessors or industrial
system applications.
Upon VDD bias power up the PGOOD output is held low
with VDD as low as 0V. Once biased to 2.7V and enabled
the IC continuously monitors from one to four voltages
independently through external resistor dividers comparing
each VMON pin voltage to an internal 0.63V reference.
Once all VMON input voltages rise above 0.63V the PGOOD
(power good) output signal is released and is pulled high via
an external pull resistor to indicate that the power conditions
have been met. The PGOOD output is an open-drain to
allow ORing of the signals and interfacing to a wide range of
logic levels.
Once any VMON input falls below 0.63V the PGOOD output
is pulled low, the VMON inputs are designed to reject fast
transients (30µs).
If less than four voltages are being monitored, connect the
unused VMON pins to VDD.
The PGOOD pin has an internal 20kpull-up to VDD
making an external pull-up resistor unnecessary.
Figure 1 illustrates the operational timing diagram.
4/5 EN/VMON INPUTS HIGH
VTH
LAST EN/VMON INPUT
TFIL
<TFIL
PGOOD OUTPUT
FIGURE 1. ISL6536A OPERATIONAL TIMING DIAGRAM
Typical Performance Curves
0.6
0.5 VMON<VMON_L2H
0.4
0.3
0.2
0.1 VMON>VMON_L2H
0
2.5 3.0 3.5
4.0
VDD BIAS VOLTAGE (V)
FIGURE 2. VDD CURRENT vs VDD VOLTAGE
5.0
0.645
0.642
0.639
0.636
0.633
0.630
0.627
2.5 3.0 3.5 4.0 4.5
VDD BIAS VOLTAGE (V)
FIGURE 3. VMON THRESHOLD vs VDD VOLTAGE
5.0
4

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ISL6536A
Typical Performance Curves (Continued)
PGOOD
EN
VMON
PGOOD
PG = 1V/DIV
EN = 1V/DIV
1µs/DIV
FIGURE 4. EN HIGH TO PGOOD
PG = 2V/DIV
VMON = 1V/DIV
1µs/DIV
FIGURE 5. VMON HIGH TO PGOOD
PGOOD
EN
EN = 1V/DIV
PG = 1V/DIV
10nS/DIV
FIGURE 6. EN LOW TO PGOOD
PGOOD
EN
EN = 1V/DIV
PG = 1V/DIV
10nS/DIV
FIGURE 8. EN LOW TO PGOOD
5
VMON
PGOOD
PGOOD = 2V/DIV
VMON = 1V/DIV
10µs/DIV
FIGURE 7. VMON LOW TO PGOOD
VMON
PGOOD
PGOOD = 2V/DIV
VMON = 1V/DIV
10µs/DIV
FIGURE 9. VMON LOW TO PGOOD